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1. 发明公开

KR1020130046171A 반도체 장치 및 이의 동작 방법 无效
标题翻译：半导体器件及其工作方法
公开(公告)号：KR1020130046171A
公开(公告)日：2013-05-07
申请号：KR1020110110582
申请日：2011-10-27
申请人： 에스케이하이닉스 주식회사
发明人： 강태규 , 송상현
IPC分类号： G11C16/20 , G11C16/06
CPC分类号： G11C16/225 , G11C16/06 , G11C16/32
摘要： PURPOSE: A semiconductor device and an operating method thereof are provided to improve the efficiency of the semiconductor device by storing only the one reset check code in an algorithm stored in a ROM. CONSTITUTION: A ROM(163) stores program, erase, read, and reset algorithms and outputs ROM data corresponding to the selected algorithm. A program counter(162) outputs a ROM address to the ROM to successively operate the selected algorithm. An internal circuit performs an operation corresponding to the selected algorithm according to a plurality of internal circuit control signals by the ROM data. A reset circuit stops a current algorithm by initializing the program counter according to a reset command and performs the reset algorithm. [Reference numerals] (161) Command input unit; (162) Program counter; (163) ROM; (164) Reset signal generation unit; (165) Command decoder; (166) Output register; (167) Glue logic
摘要翻译：目的：提供半导体器件及其操作方法，以通过仅将一个复位校验码存储在存储在ROM中的算法中来提高半导体器件的效率。构成：ROM（163）存储程序，擦除，读取和复位算法，并输出与所选算法相对应的ROM数据。程序计数器（162）将ROM地址输出到ROM以连续地操作所选择的算法。内部电路通过ROM数据根据多个内部电路控制信号执行与所选算法相对应的操作。复位电路通过根据复位命令初始化程序计数器来停止当前算法，并执行复位算法。（附图标记）（161）命令输入单元; （162）程序计数器; （163）ROM; （164）复位信号发生单元; （165）命令解码器; （166）输出寄存器; （167）胶水逻辑

2. 发明授权

KR101005155B1 불휘발성 메모리 소자 및 그 테스트 방법 失效
标题翻译：非易失性存储器件及其测试方法
公开(公告)号：KR101005155B1
公开(公告)日：2011-01-04
申请号：KR1020090041672
申请日：2009-05-13
申请人： 에스케이하이닉스 주식회사
发明人： 강태규
IPC分类号： G11C16/34 , G11C29/00 , G11C16/24
CPC分类号： G11C29/44 , G11C16/04 , G11C29/4401 , G11C29/72
摘要： 본 발명은 다수의 패턴 데이터를 저장하고, 상기 다수의 패턴 데이터 중 테스트 명령어 세트에 의해 선택되는 패턴 데이터를 출력하는 저장부; 상기 저장부로부터 출력되는 패턴 데이터에 따라 선택되는 다수의 페이지를 연속 프로그램하고, 상기 프로그램된 다수의 페이지들을 연속 독출 하여 페일이 발생된 메모리 셀이 연결되는 비트라인 정보 및 페일 비트라인 개수 정보를 제공하는 제어부를 포함하는 불휘발성 메모리 소자와 그 테스트 방법을 제시한다.
멀티 프로그램, 연속 독출, 테스트, 명령어 세트

3. 发明公开

KR1020100131717A 불휘발성 메모리 소자의 전압 제공 방법 失效
标题翻译：非挥发性存储器件的放电方法
公开(公告)号：KR1020100131717A
公开(公告)日：2010-12-16
申请号：KR1020090050446
申请日：2009-06-08
申请人： 에스케이하이닉스 주식회사
发明人： 강태규
IPC分类号： G11C16/30 , G11C16/12 , G11C5/14
CPC分类号： G11C16/30 , G11C5/14 , G11C16/08 , G11C16/12
摘要： PURPOSE: A method of supplying voltage to a non volatile memory device is provided to operate the non volatile memory device without the load to power and current by supplying a program voltage and a pass voltage. CONSTITUTION: A non-volatile memory device comprises a memory cell. The memory cell is connected to the word lines and bit lines. Operating voltages are gradually raised to a fixed voltage level. Operating voltages are raised according to the operation command.
摘要翻译：目的：提供向非易失性存储器件提供电压的方法，以通过提供编程电压和通过电压来操作非易失性存储器件而无需负载到功率和电流。构成：非易失性存储器件包括存储器单元。存储单元连接到字线和位线。工作电压逐渐上升到固定的电压电平。根据操作指令提高工作电压。

4. 发明公开

KR1020100122663A 불휘발성 메모리 소자 및 그 테스트 방법 失效
标题翻译：非挥发性记忆体装置及其测试方法
公开(公告)号：KR1020100122663A
公开(公告)日：2010-11-23
申请号：KR1020090041672
申请日：2009-05-13
申请人： 에스케이하이닉스 주식회사
发明人： 강태규
IPC分类号： G11C16/34 , G11C29/00 , G11C16/24
CPC分类号： G11C29/44 , G11C16/04 , G11C29/4401 , G11C29/72 , G11C16/10 , G11C16/26 , G11C29/025 , G11C2029/3602
摘要： PURPOSE: According to the non-volatile memory device and test method is the test command, the algorithm inspecting the fail of the memory cell is stored and itself red phosphorus test is proceed without the external host. CONSTITUTION: The memory cell array(110) comprises a plurality of memory blocks. The memory block comprises the cell string connected to a plurality of bit lines. The page buffer part(120) comprises a plurality of page buffer. The page buffer is connected to the respective even and odd bit line pair. The controller(130) controls the program of the non-volatile memory device(100), and the read out or the erase operation.
摘要翻译：目的：根据非易失性存储器件和测试方法是测试命令，存储单元的故障检测算法进行存储，本身进行红磷测试，无需外部主机。构成：存储单元阵列（110）包括多个存储块。存储块包括连接到多个位线的单元串。页面缓冲器部分（120）包括多个页面缓冲器。页缓冲器连接到相应的偶数和奇数位线对。控制器（130）控制非易失性存储器件（100）的程序，以及读出或擦除操作。

5. 发明公开

KR1020100111009A 불휘발성 메모리 소자의 동작 방법 无效
标题翻译：操作非易失性存储器件的方法
公开(公告)号：KR1020100111009A
公开(公告)日：2010-10-14
申请号：KR1020090029357
申请日：2009-04-06
申请人： 에스케이하이닉스 주식회사
发明人： 강태규
IPC分类号： G11C16/34 , G11C16/26
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/3459
摘要： PURPOSE: A method of operating a non volatile memory device is provided to improve the reliability of reading data by measuring the distribution of threshold voltage of memory cells connected to at least one word line and setting a data read voltage and a pass voltage. CONSTITUTION: A memory cell array(210) comprises memory blocks consisting of memory cells. A page buffer unit(220) comprises page buffer(PB). An X-decoder(230) selects the memory block and enables it. A voltage supply unit(240) supply the drive voltage of a program, data reading, and an erasing operation. A controller(250) programs word lines which are selected by a test command.
摘要翻译：目的：提供一种操作非易失性存储器件的方法，通过测量与至少一条字线连接的存储器单元的阈值电压分布以及设置数据读取电压和通过电压来提高读取数据的可靠性。构成：存储单元阵列（210）包括由存储器单元组成的存储器块。页缓冲器单元（220）包括页缓冲器（PB）。 X解码器（230）选择存储器块并启用它。电压供应单元（240）提供程序的驱动电压，数据读取和擦除操作。控制器（250）编程由测试命令选择的字线。

6. 发明公开

KR1020080114208A 에러 정정 기능을 갖는 불휘발성 메모리 장치의 카피투프로그램방법 无效
标题翻译：具有错误校正功能的非易失性存储器件的COPY2编程方法
公开(公告)号：KR1020080114208A
公开(公告)日：2008-12-31
申请号：KR1020070063553
申请日：2007-06-27
申请人： 에스케이하이닉스 주식회사
发明人： 강태규
IPC分类号： G11C16/34 , G11C29/42
CPC分类号： G11C16/10 , G06F11/1068 , G11C29/42 , G11C2216/14
摘要： A copy2 programming method of non-volatile memory device is provided to prevent accumulation of an error data although copy2 operation is repetitively performed by performing an error code correction function about copy2 operation. A copy2 programming method of non-volatile memory device comprises the following steps: a step for calculating a parity about a program target data(410); a step for programming the program target data and the parity in a first page of a memory cell(420); a step for determining an error generation by comparing after reading out a programmed data and the parity(430); a step for correcting an error in case of generating an error(440); and a step for storing a read out program target data in a page buffer(450).
摘要翻译：提供非易失性存储器件的copy2编程方法，以防止通过执行关于copy2操作的错误代码校正功能来重复执行复制2操作的错误数据的累积。非易失性存储器件的复制2编程方法包括以下步骤：用于计算关于节目目标数据的奇偶校验的步骤（410）; 用于对存储器单元（420）的第一页中的程序目标数据和奇偶校验进行编程的步骤; 通过在读出编程数据和奇偶校验之后比较来确定误差产生的步骤（430）; 在产生错误的情况下校正错误的步骤（440）; 以及将读出的程序目标数据存储在页面缓冲器（450）中的步骤。

7. 发明公开

KR1020100097398A 불휘발성 메모리 소자 및 그 동작 방법 失效
标题翻译：非挥发性记忆体装置及其操作方法
公开(公告)号：KR1020100097398A
公开(公告)日：2010-09-03
申请号：KR1020090016319
申请日：2009-02-26
申请人： 에스케이하이닉스 주식회사
发明人： 강태규
IPC分类号： G11C16/34 , G11C16/28
CPC分类号： G11C5/147 , G11C16/26 , G11C16/34 , G11C16/0483 , G11C16/3459
摘要： PURPOSE: A nonvolatile memory device and an operating method thereof are provided to reduce the time of analyzing a threshold voltage distribution by storing the threshold voltage distribution information of a standard memory cell and an algorithm. CONSTITUTION: A memory cell array(110) comprises memory cells connected to a word line and a bit line. The memory cells are selected with memory block units to program or read the data. A page buffer(120) includes page buffers connected to the bit line. A Y decoder(130) provides data input and output path of the page buffers. An X decoder(140) enables the selected memory blocks. A voltage provider(150) generates a high voltage for programming, reading, or erasing operations. A controller(160) controls the operation of a nonvolatile memory device(100) for programming, reading, or erasing operations.
摘要翻译：目的：提供一种非易失性存储器件及其操作方法，通过存储标准存储单元的阈值电压分布信息和算法来减少分析阈值电压分布的时间。构成：存储单元阵列（110）包括连接到字线和位线的存储单元。用存储块单元选择存储单元以对数据进行编程或读取。页面缓冲器（120）包括连接到位线的页缓冲器。 Y解码器（130）提供页缓冲器的数据输入和输出路径。 X解码器（140）启用所选择的存储器块。电压提供器（150）产生用于编程，读取或擦除操作的高电压。控制器（160）控制用于编程，读取或擦除操作的非易失性存储器件（100）的操作。

8. 发明授权

KR100769771B1 플래시 메모리 장치 및 그 소거 방법 有权
标题翻译：闪存存储器件及其擦除方法
公开(公告)号：KR100769771B1
公开(公告)日：2007-10-23
申请号：KR1020060096184
申请日：2006-09-29
申请人： 에스케이하이닉스 주식회사
发明人： 정민중 , 정병관 , 강태규
IPC分类号： G11C16/14
CPC分类号： G11C16/16 , H01L2924/0002 , H01L2924/00
摘要： A flash memory device and a method of erasing thereof are provided to improve erase operation speed by omitting a process of inputting a block address at every erase operation, by completing the whole erase operation if blocks are continuously erased and an erase operation of a last block is completed after storing an address of a first block and an address of the last block are stored. A memory cell array includes a number of blocks. An address register part stores a start block address corresponding to a first block among target blocks to be erased and a last block address corresponding to a last block. A control logic circuit outputs an erase command signal and a block selection address. A high voltage generator outputs erase operation voltages required in an erase operation according to the erase command signal. A block selection part transfers the erase voltages to a corresponding block according to the block selection address. An erase block address storing part stores the block selection address outputted from the control logic circuit. A block address comparator compares the last block address with the block selection address, and outputs an erase proceeding signal to the control logic circuit. The control logic circuit erases the target blocks to be erased as increasing the block selection address(S280) according to the erase proceeding signal until the last block address coincides with the block selection address(S270).
摘要翻译：提供闪速存储装置及其擦除方法，通过在每次擦除操作时省略输入块地址的处理来提高擦除操作速度，如果块被连续地擦除并完成最后块的擦除操作，则完成整个擦除操作在存储第一块的地址并且存储最后块的地址之后完成。存储单元阵列包括多个块。地址寄存器部分存储对应于要擦除的目标块中的第一块的起始块地址和对应于最后块的最后块地址。控制逻辑电路输出擦除命令信号和块选择地址。高电压发生器根据擦除命令信号输出擦除操作所需的擦除操作电压。块选择部件根据块选择地址将擦除电压传送到相应的块。擦除块地址存储部存储从控制逻辑电路输出的块选择地址。块地址比较器将最后一个块地址与块选择地址进行比较，并将一个擦除进行信号输出到控制逻辑电路。控制逻辑电路根据擦除进行信号擦除随着块选择地址（S280）的增加而被擦除的目标块，直到最后的块地址与块选择地址一致（S270）为止。

9. 发明授权

KR102253016B1 반도체 장치 및 그 동작 방법 有权
公开(公告)号：KR102253016B1
公开(公告)日：2021-05-17
申请号：KR1020140184551
申请日：2014-12-19
申请人： 에스케이하이닉스 주식회사
发明人： 강태규
IPC分类号： G11C11/4093 , G11C11/4096 , G11C11/4063 , G11C7/10
摘要： 자신의동작상태를설정하고이에따라회로동작을수행하는반도체장치에관한것으로, 동작모드각각에대응하는동작상태정보각각을다수의래칭부중 래칭제어신호에대응하는래칭위치에래칭하기위한정보래칭부, 및상기정보래칭부에래칭된동작상태정보에따라동작상태를설정하고회로동작을수행하는회로동작부를 구비하는반도체장치가제공된다.

10. 发明公开

KR1020160136002A 반도체 장치 및 그것의 동작 방법 审中-实审
标题翻译：半导体器件及其工作方法
公开(公告)号：KR1020160136002A
公开(公告)日：2016-11-29
申请号：KR1020150069620
申请日：2015-05-19
申请人： 에스케이하이닉스 주식회사
发明人： 강태규
IPC分类号： G11C16/08 , G11C16/16 , G11C16/34
CPC分类号： G06F12/0238 , G06F2212/7204 , G06F2212/7208 , G06F2212/7211
摘要： 본발명은반도체메모리장치및 이의동작방법에관한것으로, 본발명의실시예에따른반도체메모리장치는다수의메모리블럭을포함하는메모리부와, 상기다수의메모리블럭에대한배드블럭정보를저장하며, 어드레스신호에응답하여상기배드블럭정보를출력하는디코더부, 및대기상태에서비지상태로전환시상기배드블럭정보를수신하여 SR(Status Register) 코드를업데이트하고, 업데이트된상기 SR 코드와외부에서입력된명령어에따라제반동작을수행하도록상기메모리부 및상기디코더부를제어하기위한제어로직을포함한다.
摘要翻译：半导体存储器件包括：包括多个存储器块的存储器单元; 适用于存储关于多个存储块的坏块信息的解码器，并响应于地址信号输出坏块信息; 以及适于控制存储器单元和解码器的控制逻辑，以便当处于就绪状态的半导体存储器件进入忙状态时响应于坏块信息来更新状态寄存器（SR）代码，并且执行根据更新的SR代码和命令。

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