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    • 6. 发明公开
    • 분할된 게이트 구조를 갖는 비휘발성 메모리 셀들 및 그제조방법
    • 具有分离门结构的非挥发性记忆细胞及其制备方法
    • KR1020030078207A
    • 2003-10-08
    • KR1020020017090
    • 2002-03-28
    • 삼성전자주식회사
    • 김진우김동준조민수김대근
    • G11C16/06
    • H01L27/11556H01L27/115
    • PURPOSE: Nonvolatile memory cells having a split gate structure and a fabrication method thereof are provided, which have a spacer type floating gate formed in a trench region and a common source line overlapped with a side wall of the floating gate, and maximize a coupling ratio without regard to a coupling depth of a source region and a thickness of the floating gate. CONSTITUTION: An isolation film confines an active region(57a) by being formed on a region of a semiconductor substrate. A cell trench region(61) is formed on a part of the active region, and has a pair of first side walls parallel with a direction crossing the active region, and a pair of second side walls parallel with the active region and a bottom plane. A pair of insulated floating gates(65a) are formed on the first side walls and are separated each other. A source region is formed on the bottom plane of the cell trench region. A common source line(73) is intervened between the pair of floating gates, and is prolonged along the direction crossing the active region, and is connected to the source region electrically and passes through the inside of the isolation film. A pair of insulated word lines(77) cover the active regions adjacent to each floating gate, and are prolonged to be parallel with the common source line. And drain regions are formed on the active regions adjacent to the word lines and are located on an opposite side to the common source line. And the drain regions are spaced apart from the first side walls.
    • 目的:提供具有分离栅极结构的非易失性存储单元及其制造方法,其具有形成在沟槽区域中的间隔型浮动栅极和与浮置栅极的侧壁重叠的公共源极线,并且使耦合比 而不考虑源极区域的耦合深度和浮动栅极的厚度。 构成:隔离膜通过形成在半导体衬底的区域上而限制有源区(57a)。 在有源区域的一部分上形成有单元沟道区域(61),并且具有与与有源区域交叉的方向平行的一对第一侧壁和与有源区域平行的一对第二侧壁和底面 。 一对绝缘浮动栅极(65a)形成在第一侧壁上并彼此分离。 源区域形成在单元沟槽区域的底平面上。 公共源极线(73)介于一对浮置栅极之间,并且沿着与有源区域交叉的方向延伸,并且电连接到源极区域并通过隔离膜的内部。 一对绝缘字线(77)覆盖与每个浮动栅极相邻的有源区,并被延长以与公共源极线平行。 并且漏极区域形成在与字线相邻的有源区域上,并且位于与公共源极线相反的一侧。 并且漏极区域与第一侧壁间隔开。
    • 7. 发明公开
    • 반도체 장치의 제조 방법
    • 制造半导体器件的方法
    • KR1020030027393A
    • 2003-04-07
    • KR1020010060579
    • 2001-09-28
    • 삼성전자주식회사
    • 김광복하상록남정림김경현조민수
    • H01L27/10
    • PURPOSE: A method for fabricating a semiconductor device is provided to minimize a defect caused by a step in a polishing process by forming a conductive layer as a gate electrode and by partially etching the conductive layer in a high-stepped cell region so that the height of the conductive layer is reduced. CONSTITUTION: A gate oxide layer is formed on a semiconductor substrate having a cell region and a peripheral region. Structures whose side surface has a vertical profile are formed on the cell region. A conductive layer is continuously formed on the sidewall and upper surface of the structures, the surface of the cell region and the peripheral region. The first nitride layer pattern(120) is selectively formed only in the peripheral region. The conductive layer formed in the cell region is partially and anisotropically etched to lower the height of the conductive layer in the cell region by using the first nitride layer pattern as a mask. The second nitride layer is continuously formed on the conductive layer in the cell region and on the first nitride layer pattern in the peripheral region. The resultant structure is polished to eliminate the conductive layer formed on the structures in the cell region. The nitride layer left in the cell region and the peripheral region is removed. The conductive layer in the cell region and the peripheral region is patterned to form a gate electrode on both sidewalls of the structures while a gate line is formed in the peripheral region.
    • 目的:提供一种用于制造半导体器件的方法,以通过形成导电层作为栅电极并且通过部分地蚀刻高阶阶电池区域中的导电层来最小化由抛光工艺中的步骤引起的缺陷,使得高度 的导电层减少。 构成:在具有单元区域和周边区域的半导体基板上形成栅极氧化层。 在单元区域上形成侧面具有垂直剖面的结构。 在结构的侧壁和上表面,电池区域的表面和周边区域上连续地形成导电层。 第一氮化物层图案(120)仅在周边区域中选择性地形成。 通过使用第一氮化物层图案作为掩模,在单元区域中形成的导电层被部分地和各向异性地蚀刻以降低单元区域中的导电层的高度。 第二氮化物层连续地形成在电池区域的导电层上和周边区域中的第一氮化物层图案上。 对所得到的结构进行抛光以消除在单元区域中形成的结构上的导电层。 残留在单元区域和外围区域中的氮化物层被去除。 在单元区域和外围区域中的导电层被图案化以在结构的两个侧壁上形成栅电极,同时在周边区域中形成栅极线。
    • 8. 发明公开
    • 스택형 플래시 메모리 소자 및 그 제조방법
    • 堆叠式闪存存储器件及其制造方法
    • KR1020020078886A
    • 2002-10-19
    • KR1020010019155
    • 2001-04-11
    • 삼성전자주식회사
    • 김진호김동준이용규조민수류의열
    • H01L21/8247
    • PURPOSE: A stack-type flash memory device is provided to decrease the size of a unit cell without any difficulty of a process, by forming a control gate while using a self-align method using an insulated spacer instead of a photolithography process. CONSTITUTION: A source junction(118) is formed in a semiconductor substrate(100). A stack electrode of a stack-type structure composed of a floating gate(104a), an interlayer dielectric(106) and a control gate(108a) is symmetrically disposed on the right and left sides of the source junction, formed on the substrate by interposing the first insulation layer(102). An insulated spacer(114a) is formed on the stack electrode. A source line(120) is formed to be connected to the source junction by interposing the second insulation layer(116) between the stack electrodes. A drain junction(124) is formed in the position of the substrate corresponding to the source junction to partially overlap the stack electrode. The third insulation layer(122) is formed in an exposed surface of the stack electrode including the spacer. An insulation layer is formed on the resultant structure. A contact(128) is formed to be connected to the drain junction, penetrating the insulation layer. A bit line(130) is formed on the insulation layer to be connected to the contact.
    • 目的:通过在使用采用隔离间隔物而不是光刻工艺的自对准方法的同时形成控制栅,提供堆叠型闪速存储器件以减小单元电池的尺寸而不会有任何困难。 构成:在半导体衬底(100)中形成源极结(118)。 由浮置栅极(104a),层间电介质(106)和控制栅极(108a)组成的堆叠型结构的堆叠电极对称地设置在源极结的左右两侧,通过 插入第一绝缘层(102)。 在堆叠电极上形成绝缘间隔物(114a)。 源极线(120)通过将第二绝缘层(116)插入在堆叠电极之间而连接到源极结。 在与源极结对应的衬底的位置处形成漏极结(124),以部分地与堆叠电极重叠。 第三绝缘层(122)形成在包括间隔物的堆叠电极的暴露表面中。 在所得结构上形成绝缘层。 触点(128)形成为连接到漏极结,穿透绝缘层。 在绝缘层上形成位线(130)以连接到触点。
    • 10. 发明公开
    • 스플릿 게이트형 플래쉬 메모리소자
    • 分离式门型闪存存储器件
    • KR1020020068926A
    • 2002-08-28
    • KR1020010009325
    • 2001-02-23
    • 삼성전자주식회사
    • 김동준이용규조민수류의열
    • H01L27/115H01L29/788H01L21/8247
    • H01L27/11521H01L21/28273H01L21/76895H01L27/115H01L27/11524H01L29/42324H01L29/66825H01L29/7887
    • PURPOSE: A split gate type flash memory device is provided to reduce a resistance of a word line and prevent a short-circuit phenomenon between a drain and the word line. CONSTITUTION: The first gate insulating layer and a floating gate are formed on a semiconductor substrate. The first spacer is formed on the semiconductor substrate. The first junction region is overlapped with the first spacer. The second gate insulating layer and a word line are formed on a sidewall of the first spacer. The second spacer is formed on a sidewall of the word line. The first conductive line is contacted with the first spacer. The second junction region is overlapped with the word line and the second spacer. An interlayer dielectric(227) is deposited on the whole surface of the substrate. A contact hole(228) is formed by etching the interlayer dielectric(227). A metallic line(229) is formed by depositing and patterning a metallic layer thereon.
    • 目的:提供分闸式闪存器件,以减少字线的电阻并防止漏极与字线之间的短路现象。 构成:第一栅绝缘层和浮栅形成在半导体基板上。 在半导体衬底上形成第一间隔物。 第一接合区域与第一间隔物重叠。 第二栅极绝缘层和字线形成在第一间隔物的侧壁上。 第二间隔物形成在字线的侧壁上。 第一导线与第一间隔件接触。 第二结区域与字线和第二间隔物重叠。 层叠电介质(227)沉积在基片的整个表面上。 通过蚀刻层间电介质(227)形成接触孔(228)。 通过在其上沉积和图案化金属层来形成金属线(229)。