会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 2. 发明公开
    • 안티 퓨즈 검출 회로
    • 防电感检测电路
    • KR1020000048888A
    • 2000-07-25
    • KR1019997002907
    • 1997-10-03
    • 마이크론 테크놀로지, 인크.
    • 캐스퍼,스티븐,엘.마틴,크리스,지.
    • G11C17/18
    • G11C17/18
    • PURPOSE: An anti-fuse detecting circuit is provided to detect an anti-fuse in a programmable device by measuring a voltage on a detecting node. CONSTITUTION: An anti-fuse detecting circuit including an anti-fuses and a latch(104) comprises of cross-coupled transistors(114,124). A first anti-fuse has a flat connected to GND and a second flat connected to a n-channel transistor to gain VCC, and n-channel transistor 's drain is connected to p-channel transistor, and transistor connected to receive a bias voltage, and its drain is connected to p-channel transistor (112). The gate of transistor(112) is connected to receive a second bias voltage. P-channel transistor(114) is connected between a transistor(112) and positive voltage supply. In operation, transistors(110-124) function as a differential latch(A,B) nodes are latched to opposite states depending upon the voltage drops across anti-fuses(100,102). By programming one of the anti-fuses, the remaining anti-fuse operates as a reference circuit. The p-channel is provided so that the anti-fuse help the node(A) and node(B) be adjusted.
    • 目的:提供防熔丝检测电路,通过测量检测节点上的电压来检测可编程器件中的反熔丝。 构成:包括反熔丝的反熔丝检测电路和包括交叉耦合晶体管(114,124)的锁存器(104)。 第一个反熔丝具有连接到GND的平面,并且连接到n沟道晶体管的第二平面以增加VCC,并且n沟道晶体管的漏极连接到p沟道晶体管,并且晶体管连接以接收偏置电压 ,其漏极连接到p沟道晶体管(112)。 晶体管(112)的栅极被连接以接收第二偏置电压。 P沟道晶体管(114)连接在晶体管(112)和正电压源之间。 在操作中,晶体管(110-124)用作差分锁存器(A,B),根据反熔丝(100,102)之间的电压降,节点被锁存到相反的状态。 通过编程其中一个防熔丝,剩余的反熔丝作为参考电路工作。 提供p沟道,使得反熔丝有助于调节节点(A)和节点(B)。
    • 5. 发明公开
    • 반도체 메모리를 리페어하기 위한 장치 및 방법
    • 用于修复半导体存储器的装置和方法
    • KR1020080028441A
    • 2008-03-31
    • KR1020087001686
    • 2006-06-14
    • 마이크론 테크놀로지, 인크.
    • 마틴,크리스,지.매닝,트로이,에이.케스,브렌트
    • G11C29/00
    • G11C17/165G11C29/4401G11C29/789G11C29/802G11C29/808G11C2029/4402
    • An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address. ® KIPO & WIPO 2008
    • 用于修复半导体存储器件的装置和方法包括:第一存储单元阵列,第一冗余单元阵列和修复电路,被配置为在第一存储单元阵列中非易失性地存储指定至少一个有缺陷的存储单元的第一地址。 第一易失性高速缓存存储对应于指定所述至少一个有缺陷的存储器单元的第一地址的第一高速缓存地址。 修复电路将指定第一存储单元阵列的至少一个缺陷存储单元的第一地址分配给第一易失性高速缓存。 当第一存储器访问对应于第一高速缓存地址时,匹配电路将来自第一冗余单元阵列的至少一个冗余存储单元替换为第一存储单元阵列中的至少一个有缺陷的存储单元。 ®KIPO&WIPO 2008