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1. 发明授权

KR101853600B1 충전 공용 인버터 有权
标题翻译：为普通逆变器充电
公开(公告)号：KR101853600B1
公开(公告)日：2018-04-30
申请号：KR1020187001624
申请日：2015-06-23
申请人： 닛산 지도우샤 가부시키가이샤
发明人： 츠가와다이 , 야마가미시게하루
IPC分类号： H02M7/5387 , B60L11/18
CPC分类号： H02M7/53871 , H02J7/0052 , H02J2007/0059 , H02M1/08 , H02M7/48 , H02M7/5387 , H02P27/08 , Y02T10/7005
摘要： 배터리(70)의정극이접속되는상부아암의스위칭소자(21, 31, 41)와, 배터리(70)의부극이접속되는하부아암의스위칭소자(22, 32, 42)가접속되는아암회로와, 배터리(70)의정극에일단부를접속하는제1 콘덴서(10)와, 제1 콘덴서(10)의타단부와배터리(70)의부극사이에접속되는제2 콘덴서(11)와, 상부아암과하부아암의스위칭소자의접속점에캐소드전극을접속하는제1 다이오드(12)와, 제1 콘덴서(10)의타단부에캐소드전극을접속하는제2 다이오드(13)를구비하고, 제1 다이오드(12)의애노드전극과제2 다이오드(13)의애노드전극에외부전원(80)으로부터전력이공급된다.

2. 发明公开

KR1020090058470A 반도체 장치 有权
标题翻译：半导体器件
公开(公告)号：KR1020090058470A
公开(公告)日：2009-06-09
申请号：KR1020080122347
申请日：2008-12-04
申请人： 닛산 지도우샤 가부시키가이샤
发明人： 하야시데쯔야 , 호시마사까쯔 , 다나까히데아끼 , 야마가미시게하루
IPC分类号： H01L29/737
CPC分类号： H01L29/778 , H01L29/66068 , H01L29/66431
摘要： A semiconductor device is provided to suppress the concentration of leakage current in a corner part of the hetero bonding interface by supplying current to the end part of the hetero junction interface contacting with the gate insulating layer. A drift layer(2) is formed on the substrate region(1). In order to contact to the main surface facing the junction of the substrate region of the drift layer the hetero semiconductor region(3) is formed. The gate insulating layer(4) is formed in order to contact to the hetero bonding interface of the drift layer and hetero semiconductor region. The gate electrode(5) is formed on the gate insulating layer. The face to face facing the hetero bonding interface of the drift layer of the hetero semiconductor region, it is formed so that the source electrode(6) be connected ohmically through the contact hole (b). In the substrate region the drain electrode(7) is formed to be connected ohmically. An inter-layer insulating film(8) is formed in order to insulate the gate electrode and source electrode.
摘要翻译：提供一种半导体器件，通过向与栅极绝缘层接触的异质结界面的端部提供电流来抑制异质结界面的拐角部分中的漏电流的浓度。在衬底区域（1）上形成漂移层（2）。为了接触面向漂移层的衬底区域的接合处的主表面，形成异质半导体区域（3）。形成栅极绝缘层（4），以便与漂移层和异质半导体区域的异质结合界面接触。栅电极（5）形成在栅极绝缘层上。与异质半导体区域的漂移层的异质结合界面面对面地形成为使得源电极（6）通过接触孔（b）欧姆连接。在衬底区域中，漏电极（7）形成为欧姆连接。形成层间绝缘膜（8），以使栅电极和源电极绝缘。

3. 发明公开

KR1020080010110A 반도체 장치 및 반도체 장치의 제조 방법 无效
标题翻译：半导体器件和半导体器件的制造方法
公开(公告)号：KR1020080010110A
公开(公告)日：2008-01-30
申请号：KR1020060070161
申请日：2006-07-26
申请人： 닛산 지도우샤 가부시키가이샤
发明人： 다나까히데아끼 , 호시마사까쯔 , 시모이다요시오 , 하야시데쯔야 , 야마가미시게하루
IPC分类号： H01L29/737
CPC分类号： H01L29/6606 , H01L29/1608 , H01L29/66068
摘要： A semiconductor device and a manufacturing method thereof are provided to manufacture a diode or a switch device having high reverse pressure resistance by forming an electric field reducing area without heat treatment. A semiconductor device includes a hetero junction, and an electric field reducing area(5). The hetero junction is formed by a first semiconductor material and a second semiconductor material with the different band gap from that of the first semiconductor material. The electric field reducing area is composed of an impurities introducing area(4) formed on the first semiconductor material contacted with the hetero junction.
摘要翻译：提供半导体器件及其制造方法，通过在没有热处理的情况下形成电场减少区域来制造具有高反向耐压性的二极管或开关器件。半导体器件包括异质结和电场减少区（5）。异质结由第一半导体材料和具有与第一半导体材料的带隙不同的带隙的第二半导体材料形成。电场减少区域由形成在与异质结接触的第一半导体材料上的杂质导入区域（4）构成。

4. 发明公开

KR1020070025952A 반도체 장치 有权
标题翻译：半导体器件
公开(公告)号：KR1020070025952A
公开(公告)日：2007-03-08
申请号：KR1020060046823
申请日：2006-05-25
申请人： 닛산 지도우샤 가부시키가이샤
发明人： 시모이다요시오 , 호시마사까쯔 , 다나까히데아끼 , 하야시데쯔야 , 시노하라도시로 , 야마가미시게하루
IPC分类号： H01L29/861
CPC分类号： H01L29/7804 , H01L29/7818
摘要： A semiconductor device is provided to simplify the fabricating process of a peripheral structure by using an enhanced hetero junction diode structure. A semiconductor device comprises a switch part and a hetero junction diode. The switch part is used for controlling on/off states of current supplied to a first conductive type semiconductor base body. The hetero junction diode is used for preventing a reverse flow of the on/off currents. The switch part is formed at a first main surface of the semiconductor base body. The hetero junction diode is formed at a second main surface of the semiconductor base body. The first main surface of the semiconductor base body is opposite to the second main surface. A hetero semiconductor region(2) of the hetero junction diode is heavily doped with second conductive type ions.
摘要翻译：提供半导体器件以通过使用增强的异质结二极管结构简化外围结构的制造工艺。半导体器件包括开关部分和异质结二极管。开关部分用于控制提供给第一导电类型半导体基体的电流的开/关状态。异质结二极管用于防止导通/截止电流的反向流动。开关部形成在半导体基体的第一主面上。异质结二极管形成在半导体基体的第二主表面。半导体基体的第一主表面与第二主表面相对。异质结二极管的异质半导体区域（2）被第二导电型离子重掺杂。

5. 发明公开

KR1020130141701A 반도체 장치 및 그 제조 방법 有权
标题翻译： 반도체장치및그제조방법
公开(公告)号：KR1020130141701A
公开(公告)日：2013-12-26
申请号：KR1020137030215
申请日：2012-02-24
申请人： 닛산 지도우샤 가부시키가이샤
发明人： 야마가미시게하루 , 하야시데츠야 , 시모무라다쿠
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7801 , H01L27/0629 , H01L29/0623 , H01L29/1608 , H01L29/165 , H01L29/41766 , H01L29/4238 , H01L29/66068 , H01L29/7803 , H01L29/7805 , H01L29/7806 , H01L29/7813 , H01L29/7804
摘要： A semiconductor device is configured by forming an anode region (106) inside a drift region (102) in the bottom section of or directly below a groove (105) having a gate electrode (108) formed therein, forming a contact hole (110) inside the groove (105) to a depth that reaches the anode region (106), implanting a source electrode (112) in the contact hole (110) with an inner-wall insulating film (111) therebetween, and electrically connecting the anode region (106) and the source electrode (112) in a state where the anode region (106) and the source electrode (112) are isolated from the insulated gate electrode (108) by the inner-wall insulating film (111).
摘要翻译：通过在其中形成有栅电极（108）的沟槽（105）的底部或正下方的漂移区（102）内形成阳极区（106），形成接触孔（110）在沟槽（105）内部到达阳极区域（106）的深度处，通过其间的内壁绝缘膜（111）在接触孔（110）中注入源电极（112），并且电连接阳极区域通过内壁绝缘膜111将阳极区域106和源极电极112与绝缘栅电极108隔离的状态下，使源极电极106与源极电极112接触。

6. 发明授权

KR101036963B1 반도체 장치 제조 방법 有权
公开(公告)号：KR101036963B1
公开(公告)日：2011-05-25
申请号：KR1020107012550
申请日：2006-06-26
申请人： 닛산 지도우샤 가부시키가이샤
发明人： 야마가미시게하루 , 호시마사까쯔 , 하야시데쯔야 , 다나까히데아끼 , 시모이다요시오
IPC分类号： H01L21/18 , H01L29/24 , H01L29/267 , H01L29/78
CPC分类号： H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/7827
摘要： 다결정 실리콘층(5)을 구비한 반도체 장치 제조 방법은, 다결정 실리콘층(5) 상에 마스크층(7)을 형성하는 단계와, 마스크층(7)의 측면 상에 제공되며 다결정 실리콘층(6)의 일부를 커버하는 측벽(8)을 형성하는 단계와, 마스크층(7) 및 측벽(8) 중 적어도 하나를 마스크로서 이용하여 다결정 실리콘층(5)에 불순물(52)을 도핑하는 단계와, 마스크층(7) 및 측벽(8) 중 적어도 하나를 마스크로서 이용하여 다결정 실리콘층(5, 6)을 에칭하는 단계를 포함한다.

7. 发明公开

KR1020100068502A 반도체 장치 제조 방법 有权
标题翻译：半导体器件制造方法
公开(公告)号：KR1020100068502A
公开(公告)日：2010-06-23
申请号：KR1020107012550
申请日：2006-06-26
申请人： 닛산 지도우샤 가부시키가이샤
发明人： 야마가미시게하루 , 호시마사까쯔 , 하야시데쯔야 , 다나까히데아끼 , 시모이다요시오
IPC分类号： H01L21/18 , H01L29/24 , H01L29/267 , H01L29/78
CPC分类号： H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/7827 , H01L21/18
摘要： A method of manufacturing a semiconductor device having a polycrystalline silicon layer (5) includes; a step of forming a mask layer (7) on the polycrystalline silicon layer (5); a step of forming a side wall (8) that is provided on a side face of the mask layer (7) and covers part of the polycrystalline silicon layer (6); a step of doping an impurity into the polycrystalline silicon layer (5) by using at least one of the mask layer (7) and the side wall (8) as a mask; and a step of etching the polycrystalline silicon layer (5, 6) by using at least one of the mask layer (7) and the side wall (8) as a mask.
摘要翻译：一种制造具有多晶硅层（5）的半导体器件的方法包括：在多晶硅层（5）上形成掩模层（7）的步骤; 形成设置在掩模层（7）的侧面并覆盖多晶硅层（6）的一部分的侧壁（8）的步骤; 通过使用掩模层（7）和侧壁（8）中的至少一个作为掩模将杂质掺杂到多晶硅层（5）中的步骤; 以及通过使用掩模层（7）和侧壁（8）中的至少一个作为掩模来蚀刻多晶硅层（5,6）的步骤。

8. 发明公开

KR1020080059069A 반도체 소자 有权
标题翻译：半导体器件
公开(公告)号：KR1020080059069A
公开(公告)日：2008-06-26
申请号：KR1020070134856
申请日：2007-12-21
申请人： 닛산 지도우샤 가부시키가이샤
发明人： 하야시데쯔야 , 호시마사까쯔 , 다나까히데아끼 , 야마가미시게하루
IPC分类号： H01L29/737
CPC分类号： H01L27/088 , H01L21/32139 , H01L27/0605 , H01L29/0619 , H01L29/0623 , H01L29/1608 , H01L29/267 , H01L29/4236 , H01L29/66068 , H01L29/7828
摘要： A semiconductor device is provided to enhance reliability by reducing concentration of current to a switch structure positioned at an outermost part. A plurality of switch elements are integrated on a semiconductor chip. Each of the switch elements includes a semiconductor substrate made of a first semiconductor material, a hetero-semiconductor region(3) made of a second semiconductor material having a band gap width different from the band gap of the first semiconductor material to be hetero-adjoined with the semiconductor substrate, a gate insulation layer(4) adjoined to a heterojunction of the semiconductor substrate and the hetero semiconductor region, a gate electrode(5) adjoined to the gate insulation layer, a source electrode(6) connected to a source contact part of the hetero-semiconductor region, and a drain electrode connected to the semiconductor substrate. The switch elements include a first switch element arranged at an outermost part of the semiconductor chip and a second switch element arranged at an inner part of the semiconductor chip. The first switch element includes a mechanism in which the amount of current applied to the first switch element is smaller than the amount of current applied to the second switch element when the switch elements are in a conducting state of the current.
摘要翻译：提供半导体器件以通过减少对位于最外部的开关结构的电流的集中来提高可靠性。多个开关元件集成在半导体芯片上。每个开关元件包括由第一半导体材料制成的半导体衬底，由第二半导体材料制成的异质半导体区域（3），所述异质半导体区域（3）的带隙宽度不同于将被异质连接的第一半导体材料的带隙与所述半导体衬底相邻的栅极绝缘层（4）与所述半导体衬底和所述异质半导体区域的异质结邻接，与所述栅极绝缘层邻接的栅电极（5），连接到源极触点异源半导体区域的一部分和与半导体衬底连接的漏电极。开关元件包括布置在半导体芯片的最外部的第一开关元件和布置在半导体芯片的内部的第二开关元件。第一开关元件包括其中施加到第一开关元件的电流量小于当开关元件处于导通状态时施加到第二开关元件的电流量的机构。

9. 发明授权

KR101889249B1 전력 변환 장치 有权
公开(公告)号：KR101889249B1
公开(公告)日：2018-08-16
申请号：KR1020177035731
申请日：2015-05-29
申请人： 닛산 지도우샤 가부시키가이샤
发明人： 신겐타로 , 야마가미시게하루
IPC分类号： H02M7/00 , H05K7/20
CPC分类号： H02M1/44 , B60L11/1803 , B60L2210/40 , B60L2270/147 , H02M1/14 , H02M3/155 , H02M7/003 , H02M7/48 , H05K7/1432 , H05K7/20927
摘要： 플러스전원을공급하는제1 급전모선(10)과마이너스전원을공급하는제2 급전모선(11) 사이에설치되는파워모듈(12)과, 제1 급전모선(10)에일단부를접속하는제1 콘덴서(13a)와, 제2 급전모선(11)에일단부를접속하는제2 콘덴서(13b)와, 제1 콘덴서(13a)의타단부와제2 콘덴서(13b)의타단부사이에접속되는접지부재(13c)와, 제1 급전모선(10)과제2 급전모선(11) 중적어도한쪽을따라부설되고, 접지부재(13c)와접지전위사이를접속하는도전부재(14)를구비한다.

10. 发明公开

KR1020070106440A 반도체 장치 및 그 제조 방법 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：KR1020070106440A
公开(公告)日：2007-11-01
申请号：KR1020070041223
申请日：2007-04-27
申请人： 닛산 지도우샤 가부시키가이샤
发明人： 시모이다요시오 , 호시마사까쯔 , 하야시데쯔야 , 다나까히데아끼 , 야마가미시게하루
IPC分类号： H01L29/78
CPC分类号： H01L27/0255 , H01L28/20 , H01L29/1608 , H01L29/161 , H01L29/267 , H01L29/66068 , H01L29/7828 , H01L29/866
摘要： A semiconductor device is provided to reduce inner resistance after breakdown of an electrostatic discharge protection device by sufficiently increasing the junction area of a directional zener diode constituting the electrostatic discharge protection device. A passive device for an electrostatic discharge protection is formed on a semiconductor substrate by interposing a field insulation layer, including one or more first-layered semiconductor regions(9), one or more second-layered semiconductor regions(15), and a stacked semiconductor region having a contact region where the first-layered semiconductor region and the second-layered semiconductor region vertically overlap each other and come in contact with each other. The first-layered and second-layered semiconductor regions are divided into one or more predetermined regions of desired island shapes, electrically insulated from each other.
摘要翻译：提供一种半导体器件，通过充分增加构成静电放电保护器件的方向齐纳二极管的接合面积来减小静电放电保护器件击穿之后的内阻。通过插入包括一个或多个第一层半导体区域（9），一个或多个第二层半导体区域（15）的场绝缘层和半导体层叠体的半导体衬底，形成用于静电放电保护的无源器件区域，其具有第一层半导体区域和第二层状半导体区域彼此垂直重叠并且彼此接触的接触区域。第一层和第二层半导体区域被分成一个或多个预定的岛状形状的预定区域，彼此电绝缘。

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