专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

KR100538589B1 트윈셀을 구비한 반도체 기억 장치 失效
标题翻译：具有双单元的半导体存储器件
公开(公告)号：KR100538589B1
公开(公告)日：2005-12-22
申请号：KR1020030061964
申请日：2003-09-05
申请人： 가부시끼가이샤 르네사스 테크놀로지
发明人： 츠키카와야스히코 , 이토다카시
IPC分类号： H01L27/108
CPC分类号： H01L27/10882 , G11C7/18 , G11C11/405 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/10814
摘要： 2개의 DRAM 셀에 의해서 구성되는 트윈셀(101#)에 있어서, 각 트윈셀(101#) 마다 셀 플레이트(130#)를 전기적으로 분리한다. 이에 따라, 동일 트윈셀 내의 서로 상보 데이터를 기억하는 2개의 스토리지 노드(140)의 전압은 용량 결합에 의해서 마찬가지로 변동한다.

2. 发明公开

KR1020040067795A 트윈셀을 구비한 반도체 기억 장치 失效
标题翻译：具有双电池提供的半导体存储器件，具有改进的刷新特性
公开(公告)号：KR1020040067795A
公开(公告)日：2004-07-30
申请号：KR1020030061964
申请日：2003-09-05
申请人： 가부시끼가이샤 르네사스 테크놀로지
发明人： 츠키카와야스히코 , 이토다카시
IPC分类号： H01L27/108
CPC分类号： H01L27/10882 , G11C7/18 , G11C11/405 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/10814
摘要： PURPOSE: A semiconductor memory device is provided to improve refresh characteristics of a semiconductor memory device by electrically isolating cell plates corresponding to memory units(twin cells). CONSTITUTION: A semiconductor memory device includes a plurality of memory cells, a plurality of bit lines(BL0,BL1), a plurality of word lines(WL0¯WL6), and a plurality of cell plates(130#). The memory cells are arranged in rows and columns, and are divided into a plurality of memory units each made of the two memory cells storing complementary data. The bit lines are arranged corresponding to the columns of the memory cells and constitute pairs. The plurality of word lines are arranged corresponding to the rows of the memory cells in a direction crossing the bit lines. The plurality of cell plates are provided corresponding to the memory units respectively, and at least electrically isolated from one another. Each of the memory cells includes a select transistor and a capacitor. The select transistor is connected between the corresponding bit line and a storage nod, and is turned on or off in accordance with a voltage on the corresponding word line.
摘要翻译：目的：提供半导体存储器件，以通过电隔离对应于存储单元（双胞细胞）的单元板来改善半导体存储器件的刷新特性。构成：半导体存储器件包括多个存储单元，多个位线（BL0，BL1），多个字线（WL0WL6）和多个单元板（130＃）。存储单元被排列成行和列，并被分成多个存储器单元，每个存储单元由存储互补数据的两个存储器单元构成。位线被布置成对应于存储器单元的列并且构成对。多个字线在与位线交叉的方向上对应于存储单元的行排列。多个单元板分别对应于存储单元提供，并且至少彼此电隔离。每个存储单元包括选择晶体管和电容器。选择晶体管连接在对应的位线和存储点之间，并且根据对应字线上的电压而导通或截止。

3. 发明公开

KR1020040053753A 메모리셀이 고밀도로 배치된 반도체 기억 장치 无效
标题翻译：具有高密度的记忆细胞的半导体存储器件用于减少占用面积
公开(公告)号：KR1020040053753A
公开(公告)日：2004-06-24
申请号：KR1020030059475
申请日：2003-08-27
申请人： 가부시끼가이샤 르네사스 테크놀로지
发明人： 츠키카와야스히코
IPC分类号： H01L21/3205
CPC分类号： H01L27/10882 , G11C11/404 , G11C11/4097 , H01L27/0207 , H01L27/10885 , H01L27/10891
摘要： PURPOSE: A semiconductor memory device is provided to reduce occupied area of a memory cell in a twin-cell mode DRAM(Dynamic Random Access Memory) by minimizing the size of a basic cell region. CONSTITUTION: A plurality of memory cells(BCU) are arranged in rows and columns. Each memory cell includes a transistor and a capacitor. A plurality of bit lines(BL0-BL9) are arrayed corresponding to memory cell columns. A plurality of word lines(WL0-WL5) are arrayed corresponding to memory cell rows. The word lines cross the bit lines. Each memory cell includes an active region extending to a direction between extending directions of corresponding word and bit lines, and a storage node electrically connected to the active region. A bit line contact(BC) is used for connecting electrically the active region of each memory cell with a corresponding bit line. The bit line contact is provided to each bit line in a row direction. A word line is arranged at both sides of neighboring bit line contacts in a column direction. Each bit line contact is commonly used by two neighboring memory cells in a column direction.
摘要翻译：目的：提供一种半导体存储器件，用于通过使基本单元区域的尺寸最小化来减少双单元模式DRAM（动态随机存取存储器）中存储单元的占用面积。构成：以行和列排列多个存储单元（BCU）。每个存储单元包括晶体管和电容器。对应于存储单元列排列多个位线（BL0-BL9）。对应于存储单元行排列多个字线（WL0-WL5）。字线穿过位线。每个存储器单元包括延伸到对应字和位线的延伸方向之间的方向的有源区，以及电连接到有源区的存储节点。位线触点（BC）用于将每个存储单元的有效区域与相应的位线电连接。位线接触被提供给行方向的每个位线。在列方向上的相邻位线接点的两侧排列有字线。两个相邻存储单元在列方向上通常使用每个位线接触。

4. 发明公开

KR1020040042796A 반도체 기억 회로 无效
标题翻译：半导体存储器电路，其中进行了测试
公开(公告)号：KR1020040042796A
公开(公告)日：2004-05-20
申请号：KR1020030056309
申请日：2003-08-14
申请人： 가부시끼가이샤 르네사스 테크놀로지
发明人： 츠키카와야스히코
IPC分类号： G11C11/401
CPC分类号： G11C29/12 , G11C7/12 , G11C7/18 , G11C2029/1204 , G11C2207/002 , G11C2207/005
摘要： PURPOSE: A semiconductor memory circuit is provided to perform a burn-in test by giving a high potential difference between bit line pair even when using a thin film transistor in a sense amplifier. CONSTITUTION: The semiconductor memory circuit has a normal operation mode and a burn-in test mode, and comprises a memory cell array(1) having a plurality of memory cells(MC) arranged in a matrix. Pairs of bit lines(BL1,/BL1,BL2,/BL2) are prepared in a row of the memory cell array, and a plurality of word lines(WL) are prepared in a column of the memory cell array. The memory cells are located at a cross point of the bit line and the word line, and comprises one transistor and one condenser.
摘要翻译：目的：提供一种半导体存储器电路，用于通过在读出放大器中使用薄膜晶体管时，在位线对之间施加高电位差来执行老化测试。构成：半导体存储器电路具有正常操作模式和老化测试模式，并且包括具有以矩阵排列的多个存储单元（MC）的存储单元阵列（1）。在存储单元阵列的一行中准备一对位线（BL1，/ BL1，BL2，/ BL2），并且在存储单元阵列的列中准备多个字线（WL）。存储单元位于位线和字线的交叉点，并且包括一个晶体管和一个电容器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式