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71. 发明授权

KR100909635B1 반도체 소자의 트랜지스터 형성방법 失效
标题翻译：形成半导体器件的晶体管的方法
公开(公告)号：KR100909635B1
公开(公告)日：2009-07-27
申请号：KR1020080023999
申请日：2008-03-14
申请人： 에스케이하이닉스 주식회사
发明人： 은용석 , 김수호 , 이안배 , 서혜진
IPC分类号： H01L29/78 , H01L21/336
摘要： 본 발명의 반도체 소자의 트랜지스터 형성방법은, 반도체 기판 위에 식각정지막 패턴을 형성하는 단계; 식각정지막 패턴의 일 측면으로부터 소정 거리만큼 이격한 위치의 반도체 기판 내에 트렌치를 형성하는 단계; 트렌치 및 식각정지막 패턴을 매립하는 매립절연막을 형성하는 단계; 매립절연막을 식각하여 식각정지막 패턴 및 반도체 기판의 표면 일부를 노출시키는 단계; 노출된 식각정지막 패턴을 매립하는 반도체층을 형성하는 단계; 반도체층 및 매립절연막을 평탄화하여 반도체층을 분리하는 소자분리막을 형성하는 단계; 반도체층 및 소자분리막 위에 마스크막 패턴을 형성하는 단계; 마스크막 패턴을 식각 마스크로 반도체층을 식각하여 리세스 트렌치를 형성하는 단계; 리세스 트렌치 내의 식각정지막 패턴을 제거하는 단계; 및 리세스 트렌치와 중첩하는 게이트 스택을 형성하는 단계를 포함한다.
리세스 트렌치, 식각 정지막, 리세스 트렌치 깊이
摘要翻译：本发明的形成半导体器件的晶体管的方法包括：在半导体衬底上形成蚀刻停止膜图案; 在距所述蚀刻停止膜图案的一侧预定距离的位置处在所述半导体衬底中形成沟槽; 形成填充沟槽和蚀刻停止膜图案的掩埋绝缘膜; 蚀刻掩埋绝缘膜以暴露蚀刻停止膜图案的一部分和半导体衬底的表面; 形成用于嵌入暴露的蚀刻停止膜图案的半导体层; 形成用于平坦化半导体层和掩埋绝缘膜以分离半导体层的器件隔离膜; 在半导体层和元件隔离膜上形成掩模膜图案; 通过用掩模膜图案作为蚀刻掩模蚀刻半导体层来形成凹槽; 去除凹槽中的蚀刻停止膜图案; 并且形成与凹槽沟槽重叠的栅叠层。

72. 发明公开

KR1020090042468A 반도체소자의 폴리메탈게이트 형성방법 失效
标题翻译：在半导体器件中制作多金属栅的方法
公开(公告)号：KR1020090042468A
公开(公告)日：2009-04-30
申请号：KR1020070108243
申请日：2007-10-26
申请人： 에스케이하이닉스 주식회사
发明人： 김수호 , 은용석 , 이안배 , 서혜진
IPC分类号： H01L21/336
摘要： A method for forming a poly metal gate of a semiconductor device is provided to prevent permeation of an oxidation source in a laminate film interface in a selective oxidation process by forming a tungsten silicide film on a side wall of a metal film pattern. A gate electrode is formed on a substrate(100), and includes a conductive film pattern and a metal film pattern. A capping film(170) covers the gate electrode, and selectively reacts to the metal film pattern. A side wall of the conductive film pattern and an exposed substrate part are selectively oxidized. A step for forming the gate electrode includes a step for forming an insulation film, a conductive film, a metal film, and a hard mask film on the substrate and a step for forming a hard mask film pattern, a metal film pattern, a conductive film pattern, and an insulation film pattern.
摘要翻译：提供一种用于形成半导体器件的多金属栅极的方法，以通过在金属膜图案的侧壁上形成硅化钨膜来防止氧化源在选择性氧化工艺中的层压膜界面中的渗透。栅电极形成在基板（100）上，并且包括导电膜图案和金属膜图案。覆盖膜（170）覆盖栅电极，并且与金属膜图案选择性地反应。导电膜图案的侧壁和暴露的基板部分被选择性氧化。形成栅电极的步骤包括在基板上形成绝缘膜，导电膜，金属膜和硬掩模膜的步骤，以及用于形成硬掩模膜图案，金属膜图案，导电膜图案和绝缘膜图案。

73. 发明公开

KR1020090000880A 반도체소자의 게이트 형성방법 无效
标题翻译：在半导体器件中制造栅极的方法
公开(公告)号：KR1020090000880A
公开(公告)日：2009-01-08
申请号：KR1020070064758
申请日：2007-06-28
申请人： 에스케이하이닉스 주식회사
发明人： 이안배 , 은용석 , 김수호 , 서혜진
IPC分类号： H01L29/78
CPC分类号： H01L29/6656 , H01L21/02236 , H01L29/4941
摘要： A method for forming a gate of a semiconductor device is provided to perform a radical oxidation process so that a gate conductive film and spacer are oxidized into uniform thickness at the same time. An active area is set up by an element isolation film(110) performed on the semiconductor substrate(100) with shallow trench isolation. A gate insulating layer(120), gate conductive film, gate metal film and hard mask film are successively formed on the semiconductor substrate in which the active area is set up. The gate conductive film is formed into a polysilicon layer(130). The gate metal film is formed with including a tungsten nitride film(140) and tungsten film(150). Before the gate metal film is formed, the tungsten silicide film is formed.
摘要翻译：提供了形成半导体器件的栅极的方法，以进行自由基氧化处理，使得栅极导电膜和间隔物同时氧化成均匀的厚度。通过在具有浅沟槽隔离的半导体衬底（100）上执行的元件隔离膜（110）来建立有源区。在其中设置有效区域的半导体衬底上依次形成栅极绝缘层（120），栅极导电膜，栅极金属膜和硬掩模膜。栅极导电膜形成为多晶硅层（130）。栅极金属膜形成有包含氮化钨膜（140）和钨膜（150）。在形成栅极金属膜之前，形成硅化钨膜。

74. 发明公开

KR1020080114412A 벌브타입의 리세스 채널을 갖는 반도체소자의 형성 방법 无效
标题翻译：制作具有BULB型记忆通道的半导体器件的方法
公开(公告)号：KR1020080114412A
公开(公告)日：2008-12-31
申请号：KR1020070063938
申请日：2007-06-27
申请人： 에스케이하이닉스 주식회사
发明人： 서혜진 , 은용석 , 김수호 , 이안배
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66621 , H01L21/3086 , H01L29/1037 , H01L29/4236
摘要： A method for manufacturing a semiconductor device with a recess channel of a bulb type is provided to improve an electrical characteristic of a semiconductor device by forming a silicon oxide layer with a uniform thickness. A first trench is formed in an active region of a semiconductor substrate(100). The silicon oxide layer is formed by performing a radical oxide process in a sidewall of the first trench. A barrier spacer is formed in the sidewall of the first trench by anisotropically etching the silicon oxide layer. A second trench(130a) of a belt type which is connected to the first trench is formed by etching the semiconductor substrate of the bottom of the first trench. An insulating layer(150), a conductive layer(160), a metal layer(180), and a hard mask layer(190) are formed on the second trench. The gate stack is formed by patterning the hard mask layer, the metal layer, the conductive layer, and the insulating layer.
摘要翻译：提供一种用于制造具有灯泡型凹槽通道的半导体器件的方法，以通过形成具有均匀厚度的氧化硅层来改善半导体器件的电特性。第一沟槽形成在半导体衬底（100）的有源区中。通过在第一沟槽的侧壁中进行自由基氧化物工艺来形成氧化硅层。通过各向异性蚀刻氧化硅层，在第一沟槽的侧壁中形成阻挡间隔物。通过蚀刻第一沟槽的底部的半导体衬底来形成连接到第一沟槽的带式的第二沟槽（130a）。在第二沟槽上形成绝缘层（150），导电层（160），金属层（180）和硬掩模层（190）。栅堆叠通过图案化硬掩模层，金属层，导电层和绝缘层而形成。

75. 发明公开

KR1020080091950A 반도체 소자의 트랜지스터 제조방법 无效
标题翻译：半导体器件制造晶体管的方法
公开(公告)号：KR1020080091950A
公开(公告)日：2008-10-15
申请号：KR1020070035076
申请日：2007-04-10
申请人： 에스케이하이닉스 주식회사
发明人： 김수호 , 이안배
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823468 , H01L29/6656
摘要： A method for manufacturing a transistor in a semiconductor device is provided to compensate for temperature difference between an oxide layer forming process and a nitride forming process by moving a semiconductor substrate through a parallel loading method. A method for manufacturing a transistor in a semiconductor device includes the steps of: forming gate patterns(212a,212b) on a semiconductor substrate(200) including a cell region(A) and a peripheral circuit(B); forming a buffer layer(214) on the semiconductor substrate and the gate pattern; depositing a spacer nitride layer(216) on the buffer layer through a parallel loading method; forming a spacer oxide layer on the spacer nitride layer; forming gate spacers on both lateral sides of the gate pattern by etching the buffer layer, the nitride layer, and the spacer oxide layer selectively; forming an insulating layer on the gate pattern provided with the spacer; and depositing a cell spacer on the insulating layer through a parallel loading method.
摘要翻译：提供一种用于制造半导体器件中的晶体管的方法，以通过平行加载方法移动半导体衬底来补偿氧化物层形成工艺和氮化物形成工艺之间的温度差。一种在半导体器件中制造晶体管的方法，包括以下步骤：在包括单元区域（A）和外围电路（B）的半导体衬底（200）上形成栅极图案（212a，212b）; 在半导体衬底和栅极图案上形成缓冲层（214）; 通过平行加载方法在缓冲层上沉积间隔氮化物层（216）; 在间隔氮化物层上形成间隔氧化物层; 通过选择性地蚀刻缓冲层，氮化物层和间隔氧化物层，在栅极图案的两个侧面上形成栅极间隔物; 在设置有间隔物的栅极图案上形成绝缘层; 以及通过平行加载方法在绝缘层上沉积电池间隔物。

76. 发明公开

KR1020080062731A 반도체 소자의 듀얼 폴리게이트 및 그 형성방법 失效
标题翻译：双聚合物门及其制备半导体器件的方法
公开(公告)号：KR1020080062731A
公开(公告)日：2008-07-03
申请号：KR1020060138815
申请日：2006-12-29
申请人： 에스케이하이닉스 주식회사
发明人： 이안배 , 서혜진
IPC分类号： H01L21/336
CPC分类号： H01L21/28035 , H01L21/324 , H01L21/823828
摘要： A dual poly gate in a semiconductor device and a fabricating method thereof are provided to prevent the generation of a pin hole by giving a vertical directional stack structure to an amorphous silicon layer. A method for fabricating a dual poly gate in a semiconductor device comprises the steps of: forming a gate insulation layer(202) on a semiconductor substrate(200); fabricating a stack structure amorphous silicon layer(214) by depositing doped amorphous silicon layers(204,208,212) and undoped amorphous silicon layers(206,210) on the gate insulation layer via discontinuous supply of an impurity source with a silicon source to the semiconductor substrate; and fabricating a gate conductive layer by crystallizing the amorphous silicon via the thermal treatment on the semiconductor substrate.
摘要翻译：提供半导体器件中的双重多晶硅及其制造方法，以通过向非晶硅层提供垂直方向堆叠结构来防止产生针孔。一种在半导体器件中制造双重多晶硅栅极的方法，包括以下步骤：在半导体衬底（200）上形成栅极绝缘层（202）; 通过在所述栅极绝缘层上沉积掺杂的非晶硅层（204,208,212）和未掺杂的非晶硅层（206,210），通过用硅源向所述半导体衬底不连续地提供杂质源来制造堆叠结构的非晶硅层（214）以及通过在半导体衬底上的热处理使非晶硅结晶来制造栅极导电层。

77. 发明公开

KR1020080002596A 반도체 소자의 워드 라인 스페이서 형성 방법 失效
标题翻译：在半导体器件中制作字线间隔器的方法
公开(公告)号：KR1020080002596A
公开(公告)日：2008-01-04
申请号：KR1020060061494
申请日：2006-06-30
申请人： 에스케이하이닉스 주식회사
发明人： 김수호 , 은용석 , 이안배 , 지연혁
IPC分类号： H01L21/336
摘要： A method for forming a wordline spacer in a semiconductor device is provided to form a spacer of a uniform thickness by using as a spacer layer an amorphous silicon layer with a good step coverage and a loading effect. An insulation layer(120) for a first spacer is formed on a semiconductor substrate(100) divided into a cell region(200) and a peripheral region(210) wherein a wordline(110) is formed on the cell region and the peripheral region. An amorphous silicon layer is formed on the insulation layer for the first spacer in the cell region and the peripheral region. The amorphous silicon layer in the cell region is removed by using a barrier layer exposing the cell region. The amorphous silicon layer in the peripheral region is anisotropically etched by using a barrier layer exposing the peripheral region to form an amorphous silicon layer spacer on the lateral surface of the wordline in the peripheral region. An ion implantation process is performed on the peripheral region by using an ion implantation barrier layer as the amorphous silicon layer spacer in the peripheral region. The amorphous silicon layer spacer in the peripheral region is removed to expose the insulation layer for the first spacer. An insulation layer for a second spacer is formed on the resultant structure. The insulation layers for the first and second spacers are anisotropically etched to form a wordline spacer layer on the lateral surface of the wordline.
摘要翻译：提供了一种用于在半导体器件中形成字线间隔物的方法，通过使用具有良好阶梯覆盖和负载效应的非晶硅层作为间隔层，形成均匀厚度的间隔物。在半导体衬底（100）上形成用于第一间隔物的绝缘层（120），所述半导体衬底被划分为单元区域（200）和周边区域（210），其中在单元区域和周边区域上形成有字线。在电池区域和外围区域中的第一间隔物的绝缘层上形成非晶硅层。通过使用暴露单元区域的阻挡层来去除单元区域中的非晶硅层。通过使用暴露外围区域的阻挡层在周边区域的字线的侧面上形成非晶硅层隔离物来对外围区域中的非晶硅层进行各向异性蚀刻。通过使用离子注入阻挡层作为外围区域中的非晶硅层间隔物，对外围区域进行离子注入工艺。除去周边区域中的非晶硅层间隔物以露出用于第一间隔物的绝缘层。在所得结构上形成用于第二间隔件的绝缘层。各向异性蚀刻用于第一和第二间隔物的绝缘层，以在字线的侧表面上形成字线间隔层。

78. 发明公开

KR1020070095567A 저압화학기상증착장치를 이용한 반도체 소자의 제조방법 无效
标题翻译：使用低压化学气相沉积制造半导体器件的方法
公开(公告)号：KR1020070095567A
公开(公告)日：2007-10-01
申请号：KR1020060025852
申请日：2006-03-21
申请人： 에스케이하이닉스 주식회사
发明人： 이안배 , 은용석 , 서성민 , 조규동
IPC分类号： H01L21/205
CPC分类号： H01L21/02271 , C23C16/52 , H01L21/02164
摘要： A method for fabricating a semiconductor device in a low-pressure CMP apparatus is provided to maintain constantly a threshold voltage of the device by depositing uniformly a TEOS oxide layer on edge and center regions of a wafer. A low-pressure CMP apparatus includes an out tube(100), an inner tube(102) installed in the out tube, a boat(104) installed in the inner tube for mounting wafers, and an injector(106) introducing a source gas or a reaction gas. Pressure of the internal tube is adjusted in such a way that a first pressure and a second pressure are repeated. At that time, the source gas or reaction gas is fed through the injector to deposit an oxide layer.
摘要翻译：提供了一种在低压CMP装置中制造半导体器件的方法，以通过在晶片的边缘和中心区域均匀地沉积TEOS氧化物层来恒定地维持器件的阈值电压。低压CMP装置包括出管（100），安装在出管中的内管（102），安装在用于安装晶片的内管中的船（104），以及引入源气体或反应气体。调节内管的压力，使得重复第一压力和第二压力。此时，源气体或反应气体通过喷射器进料以沉积氧化物层。

79. 发明公开

KR1020060124398A 게이트 스페이서의 형성 방법 失效
标题翻译：制造隔板的方法
公开(公告)号：KR1020060124398A
公开(公告)日：2006-12-05
申请号：KR1020050046309
申请日：2005-05-31
申请人： 에스케이하이닉스 주식회사
发明人： 이안배
IPC分类号： H01L21/336 , H01L21/205
摘要： A method for forming a gate spacer is provided to avoid a void or thickness nonuniformity by forming a layer with a uniform thickness in a gate spacer regardless of a density of a semiconductor deposition pattern. A first temperature and an initial reaction condition of a chamber are set. Reaction gas is supplied to the chamber so that the pressure of the chamber is slowly increased to be a first pressure. The pressure and temperature are decreased to the initial reaction condition to prevent a diffusion layer from being formed. Byproducts generated from the abovementioned processes are exhausted. The foregoing processes are repeated until an oxide layer and a nitride layer formed on a semiconductor substrate become a predetermined thickness. The oxide layer and the nitride layer are etched to form a gate spacer. The first temperature is 630~640 deg.C when the chamber is a tube type and is 640~650 deg.C when the chamber is a single chamber type.
摘要翻译：提供一种用于形成栅极间隔物的方法，以避免在栅极间隔层中形成均匀厚度的层而不管半导体沉积图案的密度如何，从而避免空隙或厚度不均匀。设定室的第一温度和初始反应条件。将反应气体供应到室，使得室的压力缓慢地增加到第一压力。压力和温度降低到初始反应条件以防止形成扩散层。由上述处理产生的副产物被耗尽。重复上述处理，直到形成在半导体衬底上的氧化物层和氮化物层变为预定厚度。蚀刻氧化物层和氮化物层以形成栅极间隔物。当腔室为单腔室时，第一个温度为630〜640℃，室为管式，640〜650℃。

80. 发明授权

KR100602187B1 버티컬 퍼니스 타입의 테오스 산화막 저압화학기상증착 장비 失效
标题翻译：垂直炉型氧化铝LPCVD设备
公开(公告)号：KR100602187B1
公开(公告)日：2006-07-19
申请号：KR1020040054377
申请日：2004-07-13
申请人： 에스케이하이닉스 주식회사
发明人： 이안배 , 은용석 , 김형균
IPC分类号： C23C16/453
摘要： 본 발명은 반도체 제조 장비에 관한 것으로, 특히 산화막 증착장비에 관한 것이며, 버티컬 퍼니스(vertical furnace) 타입의 TEOS 산화막 저압화학기상증착 장비에 관한 것이다. 본 발명은 카세트에 로딩되는 더미 웨이퍼의 수를 최소화할 수 있는 버티컬 퍼니스 타입의 테오스 산화막 저압화학기상증착 장비를 제공하는데 그 목적이 있다. 본 발명에서는 버티컬 퍼니스 타입의 테오스 산화막 저압화학기상증착 장비에 연결된 TEOS 공급 라인에 가열 테이프를 적용하지 않고, TEOS 가스가 자체 분해되지 않는 최대 온도(예컨대, 600∼650℃)로 가열할 수 있는 가열 장치(예컨대, 외부 토치)를 적용한다. 이 경우, 더미 웨이퍼의 수를 최소화하고, 튜브와 가스간의 온도차에 기인한 파티클 발생을 억제할 수 있다. 한편, TEOS 가스와 함께 O
2 가스를 소오스 가스로 사용하는 경우, TEOS 가스의 공급 라인과 O
2 가스의 공급 라인을 일측 방향으로 통합시킴으로써 튜브의 매니폴드(manifold)를 단순화하고 기존에 비해 반응성을 개선할 수 있다.
테오스 산화막, 저압화학기상증착 장비, 버티컬 퍼니스, 더미 웨이퍼, 가열

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