会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 73. 发明授权
    • 반도체 메모리 장치
    • 半导体存储器件
    • KR100816728B1
    • 2008-03-27
    • KR1020060095189
    • 2006-09-28
    • 에스케이하이닉스 주식회사
    • 박상일김생환
    • G11C5/14
    • G11C5/145G11C11/406G11C11/4074G11C2211/4067G11C2211/4068
    • A semiconductor memory device is provided to decrease an off leakage current of an unselected cell array block, by applying a lower voltage than a voltage applied to a selected cell array block to the unselected cell array block. A semiconductor memory device comprises a plurality of cell array blocks(101-106). A boost voltage driving unit(201-206) supplies a boost voltage to the cell array block selectively. A control part(113) controls the operation of the boost voltage driving unit in response to a cell array block selection signal and a control signal defining a standby mode or a self refresh mode. The boost voltage driving unit supplies the boost voltage to all cell array blocks in an active mode, and supplies the boost voltage to only a selected cell array block in a standby mode or a self refresh mode, in response to the control signal and the cell array block selection signal.
    • 提供一种半导体存储器件,通过施加比施加到所选择的单元阵列块的电压更低的电压到未选择的单元阵列块来减小未选择的单元阵列块的漏电流。 半导体存储器件包括多个单元阵列块(101-106)。 升压电压驱动单元(201-206)选择性地向单元阵列块提供升压电压。 控制部分(113)响应于单元阵列块选择信号和限定待机模式或自刷新模式的控制信号来控制升压电压驱动单元的操作。 升压电压驱动单元将激活电压提供给所有的单元阵列块,并且在待机模式或自刷新模式下,根据控制信号和单元将升压电压提供给选定的单元阵列块 阵列块选择信号。
    • 74. 发明授权
    • 반도체 메모리 및 그 제어방법
    • 반도체메모리및그제어방법
    • KR100748460B1
    • 2007-08-13
    • KR1020060076946
    • 2006-08-16
    • 에스케이하이닉스 주식회사
    • 김생환
    • G11C16/08G11C29/00
    • A semiconductor memory and a control method thereof are provided to reduce current consumption by disabling cell repair judgement configuration during a refresh operation so as to minimize a refresh current. In a semiconductor memory having a plurality of normal cells and a spare cell to replace a defective cell, a refresh address counting unit(200) counts a refresh address. A first pre-decoding unit(300) pre-decodes the refresh address or a normal address. A second pre-decoding unit(400) pre-decodes the normal address. An output control unit blocks the output of the second pre-decoding unit according to the input of a refresh signal. A repair set(500) judges whether to repair the address output from the second pre-decoding unit.
    • 提供半导体存储器及其控制方法,以通过在刷新操作期间禁用单元修复判断配置来减少电流消耗,从而使刷新电流最小化。 在具有多个正常单元和备用单元以替换有缺陷单元的半导体存储器中,刷新地址计数单元(200)对刷新地址进行计数。 第一预解码单元(300)预先解码刷新地址或正常地址。 第二预解码单元(400)预解码正常地址。 输出控制单元根据刷新信号的输入来阻挡第二预解码单元的输出。 修复集(500)判断是否修复从第二预解码单元输出的地址。
    • 76. 发明授权
    • 반도체 소자의 리프래쉬 회로
    • 반도체소자의리프래쉬회로
    • KR100421904B1
    • 2004-03-10
    • KR1020010014680
    • 2001-03-21
    • 에스케이하이닉스 주식회사
    • 김생환
    • G11C11/401
    • PURPOSE: A refresh circuit of a semiconductor device and a method for the same are provided to reduce standby current by performing a control operation to refresh only a predetermined part of data. CONSTITUTION: A mode setup portion(21) outputs a mode setup signal(Pref) to indicate whether a current state is a partial refresh mode or a normal refresh mode. The mode setup signal(Pref) is determined by an external command or controlling a state of an input pin. A timer portion(22) is used for performing a periodic transition of an output state in a self refresh mode to maintain data of a DRAM. An internal clock generation portion(23) generates a clock for exchanging an internal address according to an output signal of the timer portion(22) and generates an internal clock pulse(iclk) by detecting a falling edge and a rising edge of an output signal of the timer portion(22). An internal address generation portion(24) generates an internal address(Int_add) necessary for normal refresh and partial refresh according to the internal clock pulse(iclk) and control variably an order and a range of address generation according to the mode setup signal(Pref).
    • 目的:提供半导体器件的刷新电路及其方法,以通过执行控制操作以仅刷新预定部分数据来减少待机电流。 构成:模式设置部分(21)输出模式设置信号(Pref)以指示当前状态是部分刷新模式还是正常刷新模式。 模式设置信号(Pref)由外部命令决定或控制输入引脚的状态。 定时器部分(22)用于在自刷新模式下执行输出状态的周期性转变以保持DRAM的数据。 内部时钟产生部分(23)根据定时器部分(22)的输出信号产生用于交换内部地址的时钟,并通过检测输出信号的下降沿和上升沿来产生内部时钟脉冲(iclk) 的定时器部分(22)。 内部地址生成部分(24)根据内部时钟脉冲(iclk)生成正常刷新和局部刷新所需的内部地址(Int_add),并根据模式设置信号(Pref)可变地控制地址生成的顺序和范围 )。
    • 77. 发明公开
    • 온도 감지 회로
    • 温度感应电路
    • KR1020040008540A
    • 2004-01-31
    • KR1020020042179
    • 2002-07-18
    • 에스케이하이닉스 주식회사
    • 김생환
    • G11C29/00
    • G01K1/026G01K7/425G01K15/00
    • PURPOSE: A temperature sensing circuit is provided, which selects an optimum detector among a number of detectors by predicting delay variation within a variable range according to process variables or voltage variation. CONSTITUTION: A pulse generator(100) generates a pulse signal according to a temperature sensing signal. The fourth delay circuit(200) generates a number of delay signals by delaying the above temperature sensing signal with different delay time. The fifth delay circuit(300) delays the above temperature sensing signal. A number of detectors(401,402,403,404) compare the delay signals of the fourth delay circuit with the delay signal of the fifth delay circuit and then output the comparison value according to the pulse signal. A number of pads(701,702,703,704) read the output of the detectors. And a detector outputs an optimum temperature value by comparing the temperature value read through the pads with the present temperature value.
    • 目的:提供一种温度检测电路,通过根据过程变量或电压变化预测可变范围内的延迟变化,在多个检测器中选择最佳检测器。 构成:脉冲发生器(100)根据温度感测信号产生脉冲信号。 第四延迟电路(200)通过以不同的延迟时间延迟上述温度检测信号来产生多个延迟信号。 第五延迟电路(300)延迟上述温度感测信号。 多个检测器(401,402,403,404)将第四延迟电路的延迟信号与第五延迟电路的延迟信号进行比较,然后根据脉冲信号输出比较值。 许多垫(701,702,703,704)读取检测器的输出。 并且检测器通过将通过焊盘读取的温度值与当前温度值进行比较来输出最佳温度值。
    • 78. 发明公开
    • 가상형 스태틱 랜덤 억세스 메모리장치 및 그의 구동방법
    • 虚拟SRAM装置及其驱动方法
    • KR1020020089992A
    • 2002-11-30
    • KR1020010029105
    • 2001-05-25
    • 에스케이하이닉스 주식회사
    • 김생환
    • G11C11/413
    • G11C11/406G11C11/4076
    • PURPOSE: A virtual SRAM(Static Random Access Memory) device and a method for driving the same are provided to refresh data of memory cells by using dynamic memory cells. CONSTITUTION: A memory cell array block(34) has a memory cell of a DRAM. A data input/output buffer portion(20) inputs or outputs data through DQ pads(DQ0 to DQi). An address buffer portion(22) receives address signals(A0 to Ai). A command buffer portion(24) receives command signals(/CS,/WE,/OE,/LB,/UB). A data register portion(26) stores write data received from the data input/output buffer portion(20), outputs the write data to the memory cell array block(34), stores read data received from the memory cell array block(34), and the stored read data to the data input/output buffer portion(20). An address register portion(28) stores address signals received from the address buffer portion(22) and outputs the stored address signals to the memory cell array block(34). A refresh control portion(32) precharges and refreshes the memory cell of the memory cell array block(34). A control portion(30) receives command signals(/CS,/WE,/OE,/LB,/UB) from the command buffer portion(24), the address signals(A0 to Ai) from the address buffer portion(22), data signals from the data input/output buffer portion(20), and data signals from the memory cell array block(34), and controls the data input/output buffer portion(20), the data register portion(26), the address register portion(28), the refresh control portion(32), and the memory cell array block(34).
    • 目的:提供虚拟SRAM(静态随机存取存储器)装置及其驱动方法,以通过使用动态存储单元来刷新存储器单元的数据。 构成:存储单元阵列块(34)具有DRAM的存储单元。 数据输入/输出缓冲器部分(20)通过DQ焊盘(DQ0至DQi)输入或输出数据。 地址缓冲部分(22)接收地址信号(A0至Ai)。 命令缓冲器部分(24)接收命令信号(/ CS,/ WE,/ OE,/ LB,/ UB)。 数据寄存器部分(26)存储从数据输入/输出缓冲器部分(20)接收的写数据,将写数据输出到存储单元阵列块(34),存储从存储单元阵列块(34)接收的读数据, ,并将存储的读取数据传送到数据输入/输出缓冲器部分(20)。 地址寄存器部分(28)存储从地址缓冲器部分(22)接收的地址信号,并将存储的地址信号输出到存储单元阵列块(34)。 刷新控制部分(32)预先充电和刷新存储单元阵列块(34)的存储单元。 控制部分(30)从命令缓冲器部分(24)接收来自地址缓冲器部分(22)的地址信号(A0至Ai)的命令信号(/ CS,/ WE,/ OE,/ LB,/ UB) 来自数据输入/输出缓冲器部分(20)的数据信号和来自存储单元阵列块(34)的数据信号,并且控制数据输入/输出缓冲器部分(20),数据寄存器部分(26), 地址寄存器部分(28),刷新控制部分(32)和存储单元阵列块(34)。
    • 79. 发明公开
    • 반도체 소자의 리프래쉬 회로
    • 半导体器件的刷新电路及其相关方法
    • KR1020020074723A
    • 2002-10-04
    • KR1020010014680
    • 2001-03-21
    • 에스케이하이닉스 주식회사
    • 김생환
    • G11C11/401
    • G11C11/40615G11C8/18
    • PURPOSE: A refresh circuit of a semiconductor device and a method for the same are provided to reduce standby current by performing a control operation to refresh only a predetermined part of data. CONSTITUTION: A mode setup portion(21) outputs a mode setup signal(Pref) to indicate whether a current state is a partial refresh mode or a normal refresh mode. The mode setup signal(Pref) is determined by an external command or controlling a state of an input pin. A timer portion(22) is used for performing a periodic transition of an output state in a self refresh mode to maintain data of a DRAM. An internal clock generation portion(23) generates a clock for exchanging an internal address according to an output signal of the timer portion(22) and generates an internal clock pulse(iclk) by detecting a falling edge and a rising edge of an output signal of the timer portion(22). An internal address generation portion(24) generates an internal address(Int_add) necessary for normal refresh and partial refresh according to the internal clock pulse(iclk) and control variably an order and a range of address generation according to the mode setup signal(Pref).
    • 目的:提供半导体器件的刷新电路及其方法,以通过执行仅刷新预定部分数据的控制操作来减少待机电流。 构成:模式设置部分(21)输出模式设置信号(Pref)以指示当前状态是部分刷新模式还是正常刷新模式。 模式设置信号(Pref)由外部命令确定或控制输入引脚的状态。 定时器部分(22)用于在自刷新模式下执行输出状态的周期性转变以维持DRAM的数据。 内部时钟产生部分(23)根据定时器部分(22)的输出信号产生用于交换内部地址的时钟,并且通过检测下降沿和输出信号的上升沿来产生内部时钟脉冲(iclk) 的计时器部分(22)。 内部地址生成部分(24)根据内部时钟脉冲(iclk)生成正常刷新和部分刷新所需的内部地址(Int_add),并根据模式设置信号(Pref)可变地控制地址生成的顺序和范围 )。
    • 80. 发明授权
    • 불휘발성메모리를이용한자동리페어회로
    • 使用非易失性存储器的自动修复电路
    • KR100321166B1
    • 2002-05-13
    • KR1019980026207
    • 1998-06-30
    • 에스케이하이닉스 주식회사
    • 김생환홍현성김학수
    • G11C29/00
    • 본 발명의 목적은 제어수단과, 비교수단과, 스위칭수단 및 불휘발성 메모리부를 포함하여 구성되는 불휘발성 자동 리페어회로에 있어서, 퓨즈 대신에
      불휘발성 메모리(Non-Volatile Memory)를 사용하여 라이트/리드 테스트시에 리페어 모드신호를 인에이블시켜 자동으로 리페어를 실시하도록 하는
      불휘발성 메모리를 이용한 자동 리페어회로를 제공함에 있다. 이와 같은 발명의 목적을 달성하기 위한 수단은 외부에서 입력되는 리페어 요청신호와 리페어 모드신호 및 리페어 전압에 의해 제1 내지 제4 리페어 전압(F1-F4)을 발생하여 리페어신호의 레벨을 제어하는 제어수단과; 프리차지신호에 의해 스위칭되어 전원전압을 리페어신호로 제공하는 스위칭수단과; 상기 제어수단에 의해 제어된 상기 스위칭수단에서 제공된 리페어신호를 기억시켜 출력라인을 거쳐 출력하는
      불휘발성 메모리부를 포함하여 구성된다.