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11. 发明公开

KR1020090035508A 동기 메모리 판독 데이터 캡쳐 有权
标题翻译：同步存储器读取数据捕获
公开(公告)号：KR1020090035508A
公开(公告)日：2009-04-09
申请号：KR1020097000102
申请日：2007-05-07
申请人： 컨버전트 인텔렉츄얼 프로퍼티 매니지먼트 인코포레이티드
发明人： 길링햄,피터 , 맥켄지,로버트
IPC分类号： G11C11/409 , G11C11/407 , G11C11/4076
CPC分类号： G06F13/4243 , G11C7/1066 , G11C29/50012 , G11C2207/2254
摘要： A method of snap-shot data training to determine the optimum timing of the DQS enable signal in a single read operation is provided. This is accomplished by first writing a Gray code count sequence into the memory and then reading it back in a single burst. The controller samples the read burst at a fixed interval from the time the command was issued to determine the loop-around delay. A simple truth table lookup determines the optimum DQS enable timing for normal reads. Advantageously, during normal read operations, the first positive edge of the enabled DQS signal is used to sample a counter that is enabled every time a command is issued. If the counter sample changes, indicating timing drift has occurred, the DQS enable signal can be adjusted to compensate for the drift and maintain a position centered in the DQS preamble. This technique can also be applied to a system that uses the iterative approach to determining DQS enable timing on power up. Another embodiment of the invention is a simple, low latency clock domain crossing circuit based on the DQS latched sample of the counter.
摘要翻译：提供了一种快照数据训练方法，用于在单次读取操作中确定DQS使能信号的最佳定时。这是通过首先将格雷码计数序列写入存储器，然后在单个脉冲串中读回来完成的。控制器从发出命令的时间开始以固定的时间间隔对读取脉冲串进行采样，以确定环路延迟。简单的真值表查找确定正常读取的最佳DQS使能定时。有利地，在正常读取操作期间，使能的DQS信号的第一上升沿用于对每次发出命令时启用的计数器进行采样。如果计数器样本发生变化，则指示定时漂移已经发生，可以调整DQS使能信号以补偿漂移并保持以DQS前导码为中心的位置。该技术也可以应用于使用迭代方法来确定上电时的DQS使能定时的系统。本发明的另一个实施例是基于柜台的DQS锁存样本的简单的低延迟时钟域交叉电路。

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