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1. 发明专利

JP2005524888A Method for storing video signal 审中-公开
公开(公告)号：JP2005524888A
公开(公告)日：2005-08-18
申请号：JP2003559160
申请日：2002-12-23
申请人：トムソンライセンシングソシエテアノニムThomson Licensing S.A.
发明人：ノスケライナー
IPC分类号： G06F12/00 , G06F12/04 , H04N5/907 , H04N9/896
CPC分类号： H04N9/896
摘要：ランダムアクセスメモリ（ＳＤＲＡＭ）の下流に書き込みおよび読み出しに対してそれぞれ異なる周波数を有する第２のメモリ（ＦＩＦＯ）が接続されており、書き込み中および読み出し中に同期して動作するランダムアクセスメモリを用いてビデオ信号を記憶するビデオ信号の記憶方法において、記憶すべきビデオ信号は複数のパラレルデータストリームに分割される。各データストリームは時間圧縮され、その際に圧縮データストリームがランダムアクセスメモリに対する所定の１つの書き込み‐読み出しサイクルの一部のみを占めるようにされる。ランダムアクセスメモリから読み出された各データストリームは第２のメモリを介して供給され、相互に結合されてビデオ信号を形成する。

2. 发明专利

JP3331711B2 失效
公开(公告)号：JP3331711B2
公开(公告)日：2002-10-07
申请号：JP31742793
申请日：1993-11-24
IPC分类号： H04N5/06 , H03L7/085 , H04N5/12 , H04N5/92 , H04N9/83 , H04N9/87 , H04N9/896

4. 发明专利

JP2001054136A TIME BASE ERROR CORRECTION CIRCUIT 失效
公开(公告)号：JP2001054136A
公开(公告)日：2001-02-23
申请号：JP22222999
申请日：1999-08-05
申请人： MITSUBISHI ELECTRIC CORP
发明人： KAI TOSHIHIRO , ASAMOTO YOICHI , KURISAKI KAZUHIRO , HAMADA SHINJI
IPC分类号： H04N5/956 , G11B20/10 , H04N9/896
摘要： PROBLEM TO BE SOLVED: To obtain a time base error correction circuit that has a fast response. SOLUTION: The time base error correction circuit is provided with a synchronism separator means 111 that separates the FM luminance signal component from a reproduced video signal and separates a synchronizing signal from a demodulated reproduced luminance signal, a write clock generating means 112, a read clock generating means 113, a write control means 119 that writes a sampled signal into a 1st memory 107a and a 2nd memory 107b, a read control means 120 that reads the reproduced luminance signal from the 1st memory 107a and the 2nd memory 107b, a carrier generating means 114, a demodulation means 109 that outputs 1st and 2nd color difference signals from the output of the 2nd memory 107b, and a phase error correction circuit 110 that corrects the phase error.

8. 发明专利

JPH11196381A TIME BASE CORRECTOR 失效
公开(公告)号：JPH11196381A
公开(公告)日：1999-07-21
申请号：JP36040497
申请日：1997-12-26
申请人： FOR A CO LTD
发明人： OYAGI KATSUTOSHI
IPC分类号： H04N5/956 , H04N9/896
摘要： PROBLEM TO BE SOLVED: To stably operate a time base corrector even at the time of omission of an input synchronizing signal or when there is noise by adding a function which regenerates a new synchronizing signal that is synchronously connected to an input video signal and switching a synchronizing signal or a reproduced synchronizing signal. SOLUTION: Switching circuits 7 and 8 switch and output horizontal and vertical synchronizing signals which are respectively regenerated by a synchronizing signal generator 6 according to a decision output of a decision circuit 9 which decides the mode of an input video signal from a terminal 1 in a mode as a frame synchronizer and respectively switch and output input horizontal and vertical synchronizing signals from a synchronous separation circuit 2 in a mode as a time base corrector. They are used for a synchronous circuit such as memory control via terminals 12 and 13 respectively and also, a clock is generated by a PLL circuit 4 which is synchronized with a horizontal synchronizing signal of the terminal 12 and undergoes phase control and is connected and used from a terminal 11 as a clock for an analog-digital converter, memory, etc.

9. 发明专利

JP2900369B2 失效
公开(公告)号：JP2900369B2
公开(公告)日：1999-06-02
申请号：JP14235288
申请日：1988-06-09
申请人： SONII KK
发明人： KURAIU HENRII GIRAADO , UINSENTO KAARU HARADAIN
IPC分类号： H04N11/00 , H04N7/01 , H04N7/173 , H04N7/26 , H04N7/32 , H04N7/36 , H04N7/46 , H04N9/877 , H04N9/896 , H04N11/04 , H04N11/20 , H04N11/24 , H04N7/24

10. 发明专利

JP2808981B2 失效
公开(公告)号：JP2808981B2
公开(公告)日：1998-10-08
申请号：JP14022292
申请日：1992-06-01
申请人： MATSUSHITA DENKI SANGYO KK
发明人： MATSUMOTO TOKIKAZU , KOGA FUMIAKI , KITAURA HIROSHI , INOE TAKASHI , OGAWA NOBUYUKI
IPC分类号： H04N9/85 , H04N5/956 , H04N9/89 , H04N9/896

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