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1. 发明专利

JP5869134B2 非同期ハンドシェイクベースの相互接続のためのシステムおよび方法有权
标题翻译：系统和方法，用于异步握手基于互连
公开(公告)号：JP5869134B2
公开(公告)日：2016-02-24
申请号：JP2014532034
申请日：2012-09-21
申请人：クゥアルコム・インコーポレイテッド , QUALCOMM INCORPORATED
发明人：ベンカトラマン、スブラマニアン , レビン、ジェフリー・アレキサンダー
IPC分类号： H04L25/32 , H04L25/30
CPC分类号： G06F1/12

2. 发明专利

JP3426888B2 失效
公开(公告)号：JP3426888B2
公开(公告)日：2003-07-14
申请号：JP34516696
申请日：1996-12-25
IPC分类号： H03K3/84 , H04B7/26 , H04J13/00 , H04J13/16 , H04L25/32 , H04W16/28 , H04W72/04 , H04Q7/38

3. 发明专利

JPH0779358B2 失效
公开(公告)号：JPH0779358B2
公开(公告)日：1995-08-23
申请号：JP29598988
申请日：1988-11-25
IPC分类号： H04L25/38 , H04L7/08 , H04L25/32

4. 发明专利

JPH0777386B2 失效
公开(公告)号：JPH0777386B2
公开(公告)日：1995-08-16
申请号：JP10167089
申请日：1989-04-24
IPC分类号： H03K3/02 , H03M5/08 , H04B10/07 , H04B10/079 , H04B10/524 , H04B10/54 , H04B10/556 , H04L25/32 , H04L25/49 , H04B10/00 , H04B10/08

5. 发明专利

JPS62133841A ASYNCHRONIZING SERIAL SYSTEM DATA COMMUNICATION SYSTEM 失效
公开(公告)号：JPS62133841A
公开(公告)日：1987-06-17
申请号：JP27339585
申请日：1985-12-06
申请人： YASKAWA DENKI SEISAKUSHO KK
发明人： NISHI MASAO , TAKEDA ATSUO , MOTOMURA NAOYUKI
IPC分类号： H04L25/32 , H04L25/40 , H04L25/493
摘要： PURPOSE:To attain sure data recognition by selecting an in-phase or an antiphase clock in the timing between the data transmission data of a clock having the same frequency as the data transmission speed to use a sampling clock. CONSTITUTION:DFFs 3, 4 use a clock 22 as a clock input CLK and input data 21 and delayed data 21 by a delay element 1 as a data input D. DFFs 5, 6 use an inverted clock 23 the input CLK and the data 21 and the delayed data 21 by the element 1 as the input D. An RSFF 9 outputs a clock selection signal 24 or 25, an AND circuit 10 outputs a clock 22 when the signal 24 is outputted and an AND circuit 11 outputs a clock 23 when the signal 25 is outputted. An AND circuit 11 outputs a clock 23 when the signal 25 is outputted. An OR circuit 12 outputs the clock 22 or 23 outputted from the circuits 10, 11 as a sampling clock 26 to prevent malfunction thereby applying sure data transmission.

6. 实用新型

JPS615052U 失效
公开(公告)号：JPS615052U
公开(公告)日：1986-01-13
申请号：JP8751284
申请日：1984-06-13
IPC分类号： H04B10/556 , H04B10/00 , H04B10/2507 , H04L25/03 , H04L25/32 , H04B9/00

7. 发明专利

JPS6096046A DIGITAL COMMUNICATIO SYSTEM 失效
公开(公告)号：JPS6096046A
公开(公告)日：1985-05-29
申请号：JP18474184
申请日：1984-09-05
申请人： IBM
发明人： MAIKERU ANSONII KOU
IPC分类号： H04L29/06 , G06F13/00 , H03M7/42 , H04L23/00 , H04L25/32 , H04L25/49

8. 发明专利

JPS5838040A OPTICAL TRANSMISSION AND RECEPTION CIRCUIT 失效
公开(公告)号：JPS5838040A
公开(公告)日：1983-03-05
申请号：JP13505381
申请日：1981-08-28
申请人： SUMITOMO ELECTRIC INDUSTRIES
发明人： SAKAMOTO FUKUMA
IPC分类号： H04B10/556 , H04B10/00 , H04B10/524 , H04L25/32 , H04L25/49
摘要： PURPOSE:To decrease the power consumption of a photoelectric element, by generating and transmitting a plurality of optical pulse trains corresponding to one pulse of a transmission signal, converting them into electric pulses at a receiving side and restoring them into transmission signal pulses with a delay of prescribed time. CONSTITUTION:In inputting a transmission signal pulse SD, DELTAT of width, a monostable multivibrator IC1 generates a pulse having a width determined with a resistor R1 and a capacitor C1, e.g., T1=27 mus and a monostable multivibrator IC2 is driven from the output terminal -Q. The IC2 generates a sub-pulse having 3 mus (T2=C2R2) of width to illuminate a light emission diode LED and the signal is transmitted via an optical fiber OF. The sub-pulse is transmitted for n pulses during the DELTAT with T1+T2 of period and T2/T1+T2=0.1 of duty cycle. At the receiving side, this optical pulse is converted into an electric signal, which is shaped to drive a monostable multivibrator IC3. The IC3 drives a monostable multivibrator IC4 with a pulse in which the start point of the pulse has a delay of prescribed time of C3R3=T3=60mus. The IC4 restores the pulse into the pulse, DELTAT of width, by making a pulse delay for a prescribed time as the start point and extended by C4R4=T4=57mus.

9. 发明专利

JPS5685958A BINARY CODE TRANSMISSION SYSTEM 失效
公开(公告)号：JPS5685958A
公开(公告)日：1981-07-13
申请号：JP15340379
申请日：1979-11-27
申请人： FUJITSU LTD
发明人： MURANO KAZUO , YAMAGUCHI KAZUO , MURAKAMI NORIO , TSUDA TOSHITAKA
IPC分类号： H04L25/02 , H04L25/03 , H04L25/32 , H04L25/49
摘要： PURPOSE:To easily monitor the line by the receiving side as to whether there is a fault or not, by inserting a pulse of narrow width by the reverse polarity when the same code of an asynchronous data has continued exceeding the prescribed length, in the system for transmitting a binary asynchronous data. CONSTITUTION:When the same code of an asynchronous data (a) provided to the input terminal 1 of the transmission side has continued exceeding T1, a refresh pulse of pulse width T0 which is narrower than the minimum width T of the asynchronous data is inserted by the reverse polarity. The receiving side executes decoding by disregarding the refresh pulse having relation of T>>T0, and makes it a regenerated receiving code (c). At the normal time, the refresh pulse of the reverse polarity is inserted at every T1 of the same code, and therefore, it becomes easy to monitor the line by the receiving side as to whether it is a fault or not. Moreover, since not only the transmission becomes easy due to decrease of the DC component but also the refresh pulse is inserted even if the original code continues ''0'', the AGC can be operated by detecting the level.

10. 发明专利

JPS5497315A WAVEFORM SHAPING SYSTEM OF TERNARY TRANSMISSION 失效
公开(公告)号：JPS5497315A
公开(公告)日：1979-08-01
申请号：JP459078
申请日：1978-01-19
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： MINAMI SATOSHI , HORIUCHI YOSHIO
IPC分类号： H04L25/32 , H03K5/01 , H04N1/00 , H04N1/40 , H04N1/409 , H04N1/413
摘要： PURPOSE:To improve the quality of a reproduced picture by wave-form-shaping binary signals at both transmission and reception sides having reverse relation to the variation of the input-output pulse mesial magnitude of a thin line produced by transmission characteristics on the system which transmits binary signals after ternary-converting the waveform. CONSTITUTION:Signal A is written into shift register 23 from terminal 21 by sampling clock 22. The black-signal length of the input signal is counted by black-signal counter 24, and the white-signal length by white-signal counter 25. Both counting contents are stored in memory circuits 28 and 31 respectively. By analyzing the relation between the black-signal length of memory circuit 28 and the white-signal length immediately before the black signal from memory circuit 31, analyzer circuit 32 allows a signal indicating the left edge of the black part of the screen to pass through as it is when the white-signal length is not long enough, and transmits a signal expanding the white-signal part before the rise of the black signal into black to register 23 when the white-signal length is more than 18-sampling.

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