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1. 发明专利

JP4126782B2 Electronic device equipped phase synchronization circuit and this 有权
公开(公告)号：JP4126782B2
公开(公告)日：2008-07-30
申请号：JP30752598
申请日：1998-10-28
申请人：ソニー株式会社
发明人：信久小澤 , 美穂赤秀
IPC分类号： H03L7/099 , H04N5/455 , H03D3/02 , H03D3/24 , H03L7/095 , H03L7/10 , H03L7/12
CPC分类号： H03L7/12 , H03D3/241 , H03L7/095 , H03L7/10 , H03L2207/06 , Y10S331/02

2. 发明专利

JP3827403B2 Current switch circuit and pll circuit using it 失效
公开(公告)号：JP3827403B2
公开(公告)日：2006-09-27
申请号：JP12918297
申请日：1997-05-20
申请人：富士通株式会社
发明人：邦彦後藤 , 篤松田 , 裕司瀬川
IPC分类号： H03M1/74 , H03D3/24 , H03K17/687 , H03L7/089 , H03L7/093
CPC分类号： H03D3/241 , H03K17/6872 , H03L7/0891 , H03L7/0895 , H03M1/745

3. 发明专利

JP2005348208A Phase lock circuit 审中-公开
标题翻译：相锁电路
公开(公告)号：JP2005348208A
公开(公告)日：2005-12-15
申请号：JP2004166998
申请日：2004-06-04
申请人： Sony Corp , ソニー株式会社
发明人： KATAKURA MASAYUKI
IPC分类号： G01D5/245 , H03C3/09 , H03D3/24 , H03D7/00 , H03D13/00 , H03L7/06 , H03L7/07 , H03L7/085 , H03L7/087 , H04B1/26
CPC分类号： H03C3/0966 , H03L7/07 , H03L7/085 , H03L7/087
摘要： PROBLEM TO BE SOLVED: To provide a phase lock circuit which distinguishes positive/negative frequency of a complex signal to lock a phase. SOLUTION: A second complex signal Vlo has the negative frequency of amplitude according to a feedback control signal Vc. In a complex signal processor 100, a signal according to the deviation of the complex signal obtained when this second complex signal Vlo and the first complex signal Vin are multiplied, is generated. When the second complex signal Vlo and the first complex signal are multiplied, its deviation angle becomes equal to that obtained by adding the deviation angles of these two complex signals. Accordingly, in the complex signal processor 100, the signal obtained by adding the deviation angles is generated. In the feedback unit 200, a feedback control signal Vc which operates the feedback control is generated so that the added deviation angle falls within a predetermined value. Thereby, the second complex signal Vlo is phase-locked only to the component of the positive frequency obtained by canceling by the negative frequency out of the components of the positive and negative frequencies included in the first complex signal Vin. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种区分复合信号的正/负频率以锁定相位的锁相电路。解决方案：根据反馈控制信号Vc，第二复信号Vlo具有幅度的负频率。在复信号处理器100中，产生根据当该第二复数信号Vlo和第一复数信号Vin相乘时获得的复数信号的偏差的信号。当第二复信号Vlo和第一复信号相乘时，其偏差角度与通过相加这两个复信号的偏差角获得的偏差角相等。因此，在复信号处理器100中，产生通过增加偏差角获得的信号。在反馈单元200中，产生操作反馈控制的反馈控制信号Vc，使得附加偏差角落在预定值内。由此，第二复合信号Vlo仅与包含在第一复数信号Vin中的正，负频率的分量中的负频率抵消而获得的正频率分量相位锁定。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2005318014A Pseudo lock detection circuit and method, pll circuit and clock data recovery method, communication apparatus and method, and optical disk reproducing apparatus and method 审中-公开
标题翻译： PSEUDO锁定检测电路和方法，PLL电路和时钟数据恢复方法，通信设备和方法以及光盘再现设备和方法
公开(公告)号：JP2005318014A
公开(公告)日：2005-11-10
申请号：JP2004130320
申请日：2004-04-26
申请人： Sony Corp , ソニー株式会社
发明人： ISHIDA HIRONORI , NISHIMURA TAKASHI
IPC分类号： G11B20/14 , G11B20/18 , H03D3/24 , H03L7/087 , H03L7/095 , H03L7/113 , H03L7/18 , H04L7/00 , H04L7/033 , H04L7/04
CPC分类号： H03L7/095 , G11B20/18 , H03L7/087 , H03L7/113 , H03L7/18 , H03L2207/14 , H04L7/0083 , H04L7/044
摘要： PROBLEM TO BE SOLVED: To detect a pseudo lock state when a ratio of a data rate to a clock frequency is m : n (where m ≠ 1). SOLUTION: In the pseudo lock state when the ratio of the data rate to the clock frequency is m : n (wherein m ≠ 1), a clock signal delayed for a prescribed time by a buffer 171 can take any value of (0) and (1) in order to prevent a meta-stable state in a leading edge of a data signal received by an out of period detection section 102. This is because m kinds of phase relations between the leading edge of the data signal and the clock signal exist at a uniform interval, and the out of period detection section 102 can detect a periodic deviation of the phase of a change point between the data signal and the clock signal. The technology disclosed herein is applicable to pseudo lock detection circuits, PLL circuits, communication apparatuses, or optical disk reproducing apparatuses. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：当数据速率与时钟频率的比率为m：n（其中m≠1）时，检测伪锁定状态。解决方案：在数据速率与时钟频率的比率为m：n（其中m≠1）的伪锁定状态下，由缓冲器171延迟规定时间的时钟信号可以取（ 0）和（1），以防止由周期外检测部分102接收的数据信号的前沿中的元稳定状态。这是因为数据信号的前沿和时钟信号以均匀的间隔存在，周期外检测部分102可以检测数据信号和时钟信号之间的变化点的相位的周期性偏差。这里公开的技术适用于伪锁检测电路，PLL电路，通信装置或光盘再生装置。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2004208300A Phase-locked loop demodulator and demodulation method using feedforward type tracking error compensation 审中-公开
标题翻译：相位锁定解调器和使用前向类型跟踪误差补偿的解调方法
公开(公告)号：JP2004208300A
公开(公告)日：2004-07-22
申请号：JP2003418060
申请日：2003-12-16
申请人： Agilent Technol Inc , アジレント・テクノロジーズ・インクAgilent Technologies, Inc.
发明人： KARLQUIST RICHARD K
IPC分类号： H03D3/02 , H03D3/00 , H03D3/24 , H03K7/04 , H03L7/08
CPC分类号： H03D3/248
摘要： PROBLEM TO BE SOLVED: To provide a demodulator which is appropriately operable over a wide frequency band. SOLUTION: In one embodiment, the present invention relates to a PLL phase demodulator using feedforward type error correction. The feedforward type error correction can be performed by obtaining a transmission function for calibrating an equalizer (901) to emulate a modulation response curve of a VCO In a PLL of the PLL phase modulator. In operating, the equalizer is capable of receiving a filtered and integrated version of an error signal generated by a phase detector in the PLL. The equalizer filters the received signal according to the calibrated transmission function. An output of the equalizer is supplied to an adder (903), and the equalized signal and the error signal generated by a phase detector (102) are coupled. The similar calibration including an appropriately calibrated equalizer can be used to deal with a phase tracking error in the PLL frequency demodulator. COPYRIGHT: (C)2004,JPO&NCIPI
摘要翻译：要解决的问题：提供一种在宽频带上适当操作的解调器。解决方案：在一个实施例中，本发明涉及使用前馈型纠错的PLL相位解调器。可以通过获得用于校准均衡器（901）的传输功能来仿真PLL相位调制器的PLL中的VCO的调制响应曲线来执行前馈类型纠错。在操作中，均衡器能够接收由PLL中的相位检测器产生的误差信号的滤波和集成版本。均衡器根据校准的传输功能对接收的信号进行滤波。均衡器的输出被提供给加法器（903），并且由相位检测器（102）产生的均衡信号和误差信号耦合。可以使用包括适当校准的均衡器的类似校准来处理PLL频率解调器中的相位跟踪误差。版权所有（C）2004，JPO＆NCIPI

6. 发明专利

JP2002524968A 失效
公开(公告)号：JP2002524968A
公开(公告)日：2002-08-06
申请号：JP2000569536
申请日：1999-09-03
IPC分类号： H03L7/00 , H03D3/24 , H03K5/135 , H03L7/18 , H04B20060101 , H04B1/69 , H04B14/02 , H04J3/06 , H04L7/00 , H04L7/08 , H04L25/40
摘要： A precision timing generator system (400) suitable for ultra wide band (uwb) communications. A frame reference signal (432) is produced as a function of a clock signal. A first timing generator (404) generates a coarse timing signal having a nominal period and a transition occurring at a precise temporal position with respect to the nominal period. The nominal period is a function of the frame reference signal. The temporal position is a function of a first input timing command and the clock signal. A second timing generator (408) generates at least one fine timing transition as a function of a second input timing command and the clock signal. A combiner circuit (412) uses the coarse timing signal to select one of the at least one fine timing transitions to output a precise timing signal (436), wherein the precise timing signal has a high temporal precision with respect to the frame reference signal.

7. 发明专利

JP2001508634A 失效
公开(公告)号：JP2001508634A
公开(公告)日：2001-06-26
申请号：JP52800699
申请日：1998-11-13
IPC分类号： H04L27/22 , H03D1/22 , H03D3/00 , H03D3/24 , H04L27/00 , H04L27/233 , H04L27/38

8. 发明专利

JP3021662B2 失效
公开(公告)号：JP3021662B2
公开(公告)日：2000-03-15
申请号：JP52838995
申请日：1995-04-28
IPC分类号： H03G3/20 , H03D3/00 , H03D3/24 , H03D7/16 , H03G3/30 , H04B1/30 , H04L27/14 , H04L27/22

9. 发明专利

JP2953854B2 失效
公开(公告)号：JP2953854B2
公开(公告)日：1999-09-27
申请号：JP3400992
申请日：1992-01-27
申请人： NIPPON DENKI KK
发明人： MYAZAKI SHINICHI
IPC分类号： H03D3/02 , H03D3/24

10. 发明专利

JP2864143B2 失效
公开(公告)号：JP2864143B2
公开(公告)日：1999-03-03
申请号：JP7230490
申请日：1990-03-20
申请人： FUJITSU KK
发明人： SATO TOSHUKI
IPC分类号： H03K5/19 , H03B19/16 , H03D3/24 , H03L7/095 , H04L27/00 , H04M15/00 , H04Q1/44 , H04Q1/446

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