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1. 发明专利

KR102230446B1 KR102230446B1 - Electronic device and electronic system with the same 有权
公开(公告)号：KR102230446B1
公开(公告)日：2021-03-23
申请号：KR1020140098096A
申请日：2014-07-31
申请人： 에스케이하이닉스 주식회사
发明人： 황원석
IPC分类号： H03K23/00 , H04N5/374
CPC分类号： H03K23/50 , H03K21/023
摘要： 카운트 동작을 지원하는 전자 장치 및 그를 포함하는 전자 시스템에 관한 것으로, 카운트 인에이블신호에 응답하여 홀드 제어신호를 생성하기 위한 제어 로직부; 및 상기 홀드 제어신호와 카운팅 클럭 신호에 응답하여, 카운트 구간 동안 래치 동작을 중지한 상태에서 카운트 동작을 수행하고 홀드 구간 동안 상기 카운트 동작을 중지한 상태에서 상기 래치 동작을 수행하는 카운팅부를 포함하는 전자 장치가 제공된다.

2. 发明专利

JP2011071995A Counter circuit, analog/digital converter, apparatus with counter circuit and analog/digital converter, counting method and analog/digital conversion method 有权
标题翻译：计数器电路，模拟/数字转换器，具有计数器电路和模拟/数字转换器的装置，计数方法和模拟/数字转换方法
公开(公告)号：JP2011071995A
公开(公告)日：2011-04-07
申请号：JP2010216009
申请日：2010-09-27
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIM KYUNG-MIN , KOH KYOUNG MIN , HAN YOON-SEOK
IPC分类号： H03K21/17 , H03K23/00 , H03M1/56
CPC分类号： H03K23/50 , H03K21/10 , H03K23/58 , H04N5/378
摘要： PROBLEM TO BE SOLVED: To provide a counter circuit, apparatus including the same and counting method. SOLUTION: A counter circuit includes a buffer section and a ripple counter. The buffer section generates at least one lower-bit signal by latching at least one input clock signal from an ending time point of a counting operation. The ripple counter generates a higher bit signal for sequential toggling in response to latch output signals corresponding to one of lower bit signals. The counter circuit has an improved operating speed and operating margin by carrying out counting twice or more for each cycle term of the input clock signal, the number of times of toggling the bit signal is decreased and power consumption is reduced. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种计数器电路，包括其的计数器和计数方法。解决方案：一个计数器电路包括一个缓冲区和一个纹波计数器。缓冲器部分通过从计数操作的结束时间点至少锁存一个输入时钟信号来产生至少一个低位信号。纹波计数器响应于对应于低位信号之一的锁存器输出信号而产生用于顺序切换的较高位信号。计数器电路通过对输入时钟信号的每个周期项进行两次或更多次的计数，具有改进的操作速度和操作裕度，切换位信号的次数减少，功耗降低。版权所有（C）2011，JPO＆INPIT

3. 发明专利

JPWO2006129779A1 半導体記憶装置有权
公开(公告)号：JPWO2006129779A1
公开(公告)日：2009-01-08
申请号：JP2007519076
申请日：2006-05-26
申请人：セイコーエプソン株式会社
发明人：朝内　昇 , 昇朝内 , 栄太郎大塚 , 栄太郎大塚
IPC分类号： G11C16/02
CPC分类号： G11C16/06 , G06F21/6218 , H03K23/50
摘要：半導体記憶装置10は、入力された書き込みデータが、メモリアレイ100の既存データの値以上の値である場合に、メモリアレイ100に対する入力された書き込みデータの書き込みを許容する。具体的には、インクリメントコントローラ150は、メモリアレイ100から既存データを読み出し、8ビットラッチレジスタ170にラッチされている書き込みデータと比較する。インクリメントコントローラ150は、書き込みデータの値が既存データの値以上の場合には、ライト/リードコントローラ140に対して書き込み許可信号WEN1を出力し、メモリアレイ100に対する8ビットラッチレジスタ170にラッチされている書き込みデータの書き込みを実行する。

4. 发明专利

JPS6179322A Counter circuit 失效
标题翻译：计数器电路
公开(公告)号：JPS6179322A
公开(公告)日：1986-04-22
申请号：JP20264484
申请日：1984-09-27
申请人： Toshiba Corp , Toshiba Micro Comput Eng Corp
发明人： SAKAGAMI KENJI
IPC分类号： H03K23/00 , H03K23/50
CPC分类号： H03K23/50
摘要： PURPOSE:To obtain a counter circuit which can be operated at a high speed, by providing a binary counter circuit equipped with a carry signal generating means that generates carry signals and a carry signal holding means that holds the carry signals of the carry signal generating means by a prescribed clock cycle. CONSTITUTION:A counting means 10 counts input signals from a carry signal input terminal CI synchronously to a clock signal phi. A carry signal generating means 12 inputs the counting signal of the counting means 10 and the input signals and generates carry signals. A carry signal holding means 14 does not output immediately but outputs after holding a prescribed clock cycle the carry signals of the carry signal generating means from a carry signal output terminal CO. This binary counter circuit CNTS counts input signals by means of the counting means 10 synchronously to the clock signal phi and generates the carry signals in accordance with the output signal of the counting means 10 and the input signals.
摘要翻译：目的：通过提供配备有产生进位信号的进位信号发生装置的二进制计数器电路以及保持进位信号产生装置的进位信号的进位信号保持装置，获得可以高速运行的计数器电路按规定的时钟周期。构成：计数装置10将进位信号输入端子CI的输入信号与时钟信号phi同步计数。进位信号发生装置12输入计数装置10的计数信号和输入信号，并产生进位信号。进位信号保持装置14不会立即输出，而是在从进位信号输出端子CO保持进位信号产生装置的进位信号之后以规定的时钟周期保持输出，该二进制计数器电路CNTS通过计数装置10对输入信号进行计数与时钟信号phi同步，并根据计数装置10的输出信号和输入信号产生进位信号。

5. 发明专利

JP5586399B2 Counter circuit 有权
公开(公告)号：JP5586399B2
公开(公告)日：2014-09-10
申请号：JP2010216009
申请日：2010-09-27
申请人：三星電子株式会社Samsung Electronics Co.,Ltd.
发明人：敬ミン金 , 京民高 , ユンソク韓
IPC分类号： H03K21/17 , H03K23/00 , H03M1/56
CPC分类号： H03K23/50 , H03K21/10 , H03K23/58 , H04N5/378

6. 发明专利

JP2009278604A Counter of semiconductor device 有权
标题翻译：半导体器件计数器
公开(公告)号：JP2009278604A
公开(公告)日：2009-11-26
申请号：JP2008206663
申请日：2008-08-11
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： LIM SANG OH , JEONG BYOUNG KWAN , YOON MI SUN
IPC分类号： H03K23/00 , H03K23/40
CPC分类号： H03K23/40 , H03K23/50
摘要： PROBLEM TO BE SOLVED: To provide a counter, which reduces propagation time delay of the counter and minimizes data skew.
SOLUTION: An n-bit counter includes n counter blocks each including: a D-flipflop; a second MUX which selects any one of external data and a second output signal of the D-flipflop in response to a data load signal and outputs a selected signal; and a first MUX which transfers any one of a first output signal of the D-flipflop and the output signal of the second MUX as an input signal of the D-flipflop in response to a counter enable signal or the data load signal. Here. an mth counter block outputs an mth bit signal, which is toggled in a period where all output signals of second MUXs included in first to (m-1)th counter blocks are at a first level and the counter enable signal is at a second level.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种减少计数器的传播时间延迟并最小化数据偏移的计数器。解决方案：n位计数器包括n个计数器块，每个计数器块包括：D触发器; 第二MUX，响应于数据负载信号选择D触发器的外部数据和第二输出信号中的任何一个，并输出所选择的信号; 以及第一MUX，其响应于计数器使能信号或数据负载信号，将D触发器的第一输出信号和第二MUX的输出信号中的任何一个传送到D触发器的输入信号。这里。第m计数器块输出在第一到第（m-1）个计数器块中包括的第二MUX的所有输出信号处于第一电平并且计数器使能信号处于第二电平的时段内切换的第m位信号。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2003309466A Resetable cascadable divide-by-two circuit 审中-公开
标题翻译：可复位的二分法电路
公开(公告)号：JP2003309466A
公开(公告)日：2003-10-31
申请号：JP2003099555
申请日：2003-04-02
申请人： Northrop Grumman Corp , ノースロップ・グラマン・コーポレーション
发明人： CHU PETER F
IPC分类号： H03K21/00 , H03K23/00 , H03K23/50 , H03L7/089 , H03L7/183
CPC分类号： H03K23/50 , H03L7/0895 , H03L7/183
摘要： PROBLEM TO BE SOLVED: To provide a cascadable divide-by-two binary counter circuit for use as a synchronous divider circuit in a phase lock loop.
SOLUTION: This binary counter circuit 120 is composed of a D-FF (D flip- flop) 122 and cascaded. An AND gate 124 is responsive to an output Q from the counter circuit of the preceding stage and an output P dependent upon outputs of all of the counter circuits of the preceding stage and supplies an output to an exclusive-OR gate 126. The exclusive-OR gate 126 also receives an output of the FF 122 and supplies an exclusive-OR output to an AND gate 128. An output of the AND gate 128 is supplied to a D input of the FF 122. A reset signal to the AND gate 128 is generated by an appropriate decoder.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种用于在锁相环中作为同步分频器电路的可级联的二分之二二进制计数器电路。
解决方案：该二进制计数器电路120由D-FF（D触发器）122和级联组成。与门124响应于来自前级的计数器电路的输出Q和取决于前级的所有计数器电路的输出的输出P，并将输出提供给异或门126。或门126还接收FF 122的输出，并将异或输出提供给与门128.与门128的输出被提供给FF 122的D输入。复位信号到与门128 由适当的解码器产生。版权所有（C）2004，JPO

8. 发明专利

JPS60194826A Counter 失效
标题翻译：计数器
公开(公告)号：JPS60194826A
公开(公告)日：1985-10-03
申请号：JP5154484
申请日：1984-03-17
申请人： Nippon Signal Co Ltd:The
发明人： YOMOGIHARA KOUICHI
IPC分类号： H03K21/40 , H03K23/50
CPC分类号： H03K23/50
摘要： PURPOSE:To attain fail safe by using an AND arithmetic oscillator from which no output is generated because of circuit fault and a delay circuit whose delay time is not decreased even at a fault to eliminate an output or prolong a time in which the final output is generated with simple constitution at a fault. CONSTITUTION:An input pulse whose pulse width is not prolonged at a fault is inputted to AND arithmetic oscillators OSC1-OSC3 from a generator 1. The AND arithmetic oscillators OSC1-OSC3 produce no output at a fault. The output of them is rectified by rectifier circuits RC1-RC3, inputted to the next stage through delay circuits DE11-DE21 and fed back to themselves, the self holding is applied and the count is attained. Since the output is lost without fail at a fault or the time when the final output is generated is prolonged, the fail safe is attained for the counter.
摘要翻译：目的：通过使用由于电路故障而不产生输出的AND运算振荡器以及即使在故障时延迟时间也不减小的延迟电路来达到故障安全，以消除输出或延长最终输出的时间以简单的构成在故障中产生。构成：脉冲宽度不延长的输入脉冲从发生器1输入到AND运算振荡器OSC1-OSC3。与运算振荡器OSC1-OSC3在故障时不产生输出。其输出由整流电路RC1-RC3整流，通过延迟电路DE11-DE21输入到下一级，并将其反馈给自身，施加自保持并获得计数。由于输出在故障时丢失或产生最终输出的时间延长，因此计数器可以达到故障安全。

9. 发明专利

JP5024042B2 Semiconductor memory device 有权
公开(公告)号：JP5024042B2
公开(公告)日：2012-09-12
申请号：JP2007519076
申请日：2006-05-26
申请人：セイコーエプソン株式会社
发明人：栄太郎大塚 , 昇朝内
IPC分类号： G11C16/02 , G06F12/16
CPC分类号： G11C16/06 , G06F21/6218 , H03K23/50

10. 发明专利

JP2010187356A Frequency divider circuit 审中-公开
标题翻译：频率分路电路
公开(公告)号：JP2010187356A
公开(公告)日：2010-08-26
申请号：JP2009166390
申请日：2009-07-15
申请人： Sanyo Electric Co Ltd , Sanyo Semiconductor Co Ltd , 三洋半導体株式会社 , 三洋電機株式会社
发明人： TERADA SATOSHI , KOFUCHI MASAHIRO , MAKABE TADAHIRO
IPC分类号： H03K23/54 , H03K23/00 , H03K23/40
CPC分类号： H03K23/40 , H03K21/12 , H03K23/50 , H03K23/667 , H03K23/68
摘要： PROBLEM TO BE SOLVED: To provide a frequency divider circuit capable of suppressing generation of a signal of an unwanted frequency.
SOLUTION: The frequency divider circuit includes: a shift register capable of storing at least n-bit data configured to shift an input signal sequentially in synchronization with a clock signal; a pulse generating circuit configured to change the input signal into a pulse form in response to a change in logic level of an output signal from a stage of the shift register among n-bit output signals from the shift register, the stage corresponding to a bit resulting from shifting of the input signal by n bits; and a frequency dividing signal generating circuit configured to generate a frequency dividing signal whose logic level is inverted in response to a change in logic level of an output signal from any one stage of the shift register or logic level of the input signal, in order to divide the clock signal in frequency by a dividing ratio corresponding to the n bits.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够抑制不想要的频率的信号的产生的分频器电路。解决方案：分频器电路包括：移位寄存器，其能够至少存储配置成与时钟信号同步地顺序移位输入信号的n位数据; 脉冲发生电路，被配置为响应于来自移位寄存器的n位输出信号中的来自移位寄存器的级的输出信号的逻辑电平的变化而将输入信号改变为脉冲形式，对应于位由输入信号移位n位导致的; 以及分频信号生成电路，其被配置为生成分频信号，该分频信号的逻辑电平响应于来自移位寄存器的任何一个级的输出信号或输入信号的逻辑电平的逻辑电平的变化而被反转，以便将时钟信号的频率除以与n位对应的分频比。版权所有（C）2010，JPO＆INPIT

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