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1. 发明专利

JP2017112478A 静電気保護回路、半導体集積回路装置、及び、電子機器审中-公开
公开(公告)号：JP2017112478A
公开(公告)日：2017-06-22
申请号：JP2015244928
申请日：2015-12-16
申请人：セイコーエプソン株式会社
发明人：池田益英
IPC分类号： H01L21/822 , H01L27/04 , H03K17/16 , H03K19/003
CPC分类号： H01L27/0248 , H01L27/0251 , H01L27/0635 , H01L29/7408 , H01L29/7412 , H01L29/742 , H02H9/046
摘要：【課題】特殊なプロセス工程を必要とすることなく、比較的任意にトリガー電圧を設定することが可能で、通常動作時のリーク電流が小さい静電気保護回路を提供する。【解決手段】この静電気保護回路は、第1の端子に第1のノードを介して接続されると共に、第2の端子に第2のノードを介して接続された静電気保護回路であって、(i)第1のノードと第2のノードとの間に直列に接続されたトランジスター、所定数のダイオード、及び、インピーダンス素子を含む直列回路であって、トランジスターのソースとバックゲートとの間に、少なくとも所定数のダイオードが接続された直列回路と、(ii)第1のノードが第2のノードよりも高電位になって直列回路に電流が流れるときに、インピーダンス素子の両端に発生する電位差の増大に従って第1のノードから第2のノードに電流を流す放電回路とを備える。【選択図】図3

2. 发明专利

JPS5724560A Thyristor 失效
标题翻译： THYRISTOR
公开(公告)号：JPS5724560A
公开(公告)日：1982-02-09
申请号：JP9953380
申请日：1980-07-21
申请人： Nec Corp
发明人： TAKAHASHI HIROSUKE
IPC分类号： H01L29/74
CPC分类号： H01L29/7408
摘要： PURPOSE:To obtain a thyristor for small current, having a trigger current designed freely, by a method wherein a semi-short-circuited condition is formed by covering the exposed surface of the P-N junction between a gate layer and a cathode layer of the thyristor with a polycrystalline layer including impurities. CONSTITUTION:Four semiconductor layers of P1-N1-P2-N2 are formed in a semicondutor piece 1. On the P2-N2 layer surfaces of the semiconductor piece 1, monosilane (SiH4) and a impurity source are introduced to deposit a polycrystalline layer including impurities at a temperature of less than 700 deg.C by using the CVD process. Only the P2-N2 junction surface of the polycrystalline layer is protected with wax or the like, and the remaining surface is dissolved and removed with a mixed acid including hydrofluoric acid and nitric acid to form another polycrystalline layer 2. Because the polycrystalline layer is formed at low-temperature, the impurities are not diffused, the intermediate connection between a diffused junction and a resistance junction is obtained, and the shunt component of the gate current is regulated by controlling the dimensions of the layer 2.
摘要翻译：目的：为了获得具有自由设计的触发电流的小电流晶闸管，通过覆盖晶闸管的栅极层和阴极层之间的PN结的暴露表面形成半短路状态的方法，具有包含杂质的多晶层。构成：在半导体片1中形成P1-N1-P2-N2的四个半导体层。在半导体片1的P2-N2层表面上，引入单硅烷（SiH4）和杂质源沉积多晶层，通过使用CVD法在低于700℃的温度下的杂质。只有多晶层的P2-N2结面用蜡等保护，剩下的表面用包含氢氟酸和硝酸的混合酸溶解并除去，形成另一个多晶层2.因为多晶层形成在低温下，杂质不扩散，可以获得扩散结和电阻结之间的中间连接，通过控制层2的尺寸来调节栅极电流的分流分量。

3. 发明专利

KR102224471B1 KR102224471B1 - Power semiconductor device 有权
公开(公告)号：KR102224471B1
公开(公告)日：2021-03-05
申请号：KR1020150000491A
申请日：2015-01-05
申请人： 세미크론 엘렉트로니크 지엠비에치 앤드 코. 케이지
发明人： 발터 크리스티안
IPC分类号： H01L27/06 , H01L29/66 , H01L29/74
CPC分类号： H01L27/0617 , H01G2/02 , H01G2/06 , H01G4/38 , H01G9/26 , H01L25/072 , H01L25/16 , H01L29/66325 , H01L29/7408 , H05K7/1432 , H01L2224/291 , H01L2224/32225 , H01L23/04 , H01L2924/0002 , H01L2924/13055 , H01L2924/13091
摘要： 본 발명은, 전력 반도체 부품들을 포함하고 기체(basic body)를 포함하고 복수의 커패시터들을 포함하는 전력 반도체 디바이스로서, 전력 반도체 디바이스는 커패시터들 위로 끌어당겨진 일체형 프레임 장치, 및 일체형 클램프 장치를 갖는,
커패시터 체결 장치를 가지며, 프레임 장치는 긴 절결부들을 갖는 프레임 요소들을 가지며, 절결부들로 인해, 프레임 요소들 각각은 각각의 커패시터를 측면으로 에워싸는 프레임 요소 핑거들을 형성하며, 클램프 장치는, 프레임 요소 핑거들 위로 끌어당겨진 클램프 요소들을 가지며, 이들 각각은 각각의 프레임 요소의 프레임 요소 핑거들을 측면으로 둘러싸며, 클램프 요소들 및 프레임 요소 핑거들은 각각의 클램프 요소가 각각의 커패시터를 향한 방향으로 각각의 프레임 요소 핑거들에 대해 누르고 각각의 프레임 요소 핑거들이 각각의 커패시터에 대해 측면으로 누르게 하는 기하학적 형태를 가지며, 커패시터 체결 장치는 기체에 연결되는, 전력 반도체 디바이스에 관한 것이다. 발명은 전력 반도체 디바이스의 커패시터가 확실하고 신뢰성 있게 체결되고 커패시터의 체결이 거의 복잡성 없이 경제적으로 실현될 수 있는 전력 반도체 디바이스를 제공한다.

4. 发明专利

JPS5968971A Thyristor 失效
标题翻译：晶闸管
公开(公告)号：JPS5968971A
公开(公告)日：1984-04-19
申请号：JP17933082
申请日：1982-10-13
申请人： Fuji Electric Co Ltd
发明人： WADA KAZUHISA
IPC分类号： H01L29/744 , H01L29/74
CPC分类号： H01L29/7408 , H01L29/7428
摘要： PURPOSE:To obtain an amplification gate structural SCR of a high dv/dt strength which has a uniform shunt resistance without damaging an ignition characteristic by a method wherein an oxide film adjusted at a fixed resistance value is inserted between the electrodes of the main and auxiliary SCR parts by CVD method. CONSTITUTION:The main and auxiliary SCR parts 2 and 3 are formed in an Si substrate 1, and an SiO2 film 11 is left by covering the P-N junction between the N-emitter and the P-base of the SCR2. The SiO2 film 12 is provided, between the main and auxiliary electrodes 5 and 6, on the film 11 by low temperature CVD method, the gas which contains a donor impurity is mixed with a reaction gas, and thus the resistance of the film 12 is adjusted at 0.1-10OMEGA. The film 12 operates as a shunt resistor to a displacement current. Besides the ability to reduce the dispersion by adjusting the resistance values for every SCR, the initial ignition length of the emitter layer of the main SCR does not shorten because of the interposition of the insulation film 11, further the ignition junction between the base layer is protected thickly and is not influenced by external atmosphere. This constitution enables to obtain the SCR of high both strengths di/dt and dv/dt.
摘要翻译：目的：为了获得具有均匀分流电阻而不损害点火特性的高dv / dt强度的放大门结构SCR，其中将调整为固定电阻值的氧化膜插入主辅助电极之间的方法 SCR部件采用CVD法。构成：主要和辅助SCR部件2和3形成在Si衬底1中，并且通过覆盖SCR2的N发射极和P基极之间的P-N结而留下SiO 2膜11。 SiO 2膜12通过低温CVD法在主电极5,6和辅助电极6之间设置在膜11上，含有施主杂质的气体与反应气体混合，因此膜12的电阻为调整为0.1-10OMEGA。胶片12作为位移电流的分流电阻工作。除了通过调整每个SCR的电阻值来减小色散的能力之外，由于绝缘膜11的插入，主SCR的发射极层的初始点火长度也不会缩短，基底层之间的点火结不受外界环境的影响。该结构能够获得高的双重强度di / dt和dv / dt的SCR。

5. 发明专利

JPS5743462A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS5743462A
公开(公告)日：1982-03-11
申请号：JP9957481
申请日：1981-06-29
申请人： Toshiba Corp
发明人： AZUMA MINORU
IPC分类号： H01L29/74 , H01L29/744
CPC分类号： H01L29/744 , H01L29/7408
摘要： PURPOSE:To increase the current capacity of a GTO (gate turn-off thyristor) by providing a polycrystalline semiconductor layer (a resistance layer) on the first emitter region. CONSTITUTION:A polycrystalline semiconductor layer 21b is formed by a CVD method on the surface of the n type layer 21c of a wafer diffused in n 21-p22-n 23-p24 configuration, and an n type layer 21a is further formed thereon so as to anable ohmic contact. When a polycrystalline semiconductor layer (a resistance layer) is consequently formed on the first emitter region 21, the anode currents of the respective GTO elements can be, when a plurality of GTO elements are operated in parallel, remarkably averaged, and the current capacity of the GTO can be accordingly increased. The current concentration at the turning off time is positively fed back, but since the current concentrated due to the existence of the resistance of an amitter region can be, when the current concentration occurs, dispersed, it displays the same effect as of introducing a negative feedback mechanism.
摘要翻译：目的：通过在第一发射极区域提供多晶半导体层（电阻层）来增加GTO（栅极截止晶闸管）的电流容量。构成：通过CVD法在n + 21-p22-n 23-p24构型中扩散的晶片的n +型层21c的表面上形成多晶半导体层21b，n 在其上进一步形成<+>型层21a以便可以进行欧姆接触。当在第一发射极区域21上形成多晶半导体层（电阻层）时，各个GTO元件的阳极电流可以是当多个GTO元件并联操作时显着平均，而当前容量可以相应地增加GTO。关断时的电流浓度被正反馈，但是由于由于存在电流集中而产生的电流集中的电流可以是当电流浓度发生时分散，因此显示与引入负极的电流相同的效果反馈机制。

6. 发明专利

JP6052068B2 半導体装置の保護回路有权
标题翻译：的半导体装置的保护电路
公开(公告)号：JP6052068B2
公开(公告)日：2016-12-27
申请号：JP2013120711
申请日：2013-06-07
申请人：株式会社デンソー
发明人：小山和博
IPC分类号： H01L21/822 , H01L27/04 , H01L21/338 , H01L29/778 , H01L29/812 , H02M1/00 , H03K17/08
CPC分类号： H02H7/003 , H01L27/0248 , H01L29/7408 , H01L29/7412 , H01L29/778 , H03K17/08122

7. 发明专利

JP4708699B2 scr type of switch that is the high-frequency control 有权
公开(公告)号：JP4708699B2
公开(公告)日：2011-06-22
申请号：JP2003404624
申请日：2003-12-03
申请人：エステーミクロエレクトロニクスソシエテアノニム
发明人：ペザーニロベール
IPC分类号： H01L29/74 , H03K17/567 , H03K17/72 , H03K17/722
CPC分类号： H03K17/722 , H01L29/7408 , H03K17/567

9. 发明专利

JPS5969970A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS5969970A
公开(公告)日：1984-04-20
申请号：JP18187082
申请日：1982-10-15
申请人： Nec Home Electronics Ltd
发明人： NAKAMURA YOSHIHIDE , ASANO KENJIROU
IPC分类号： H01L29/74
CPC分类号： H01L29/7408
摘要： PURPOSE:To control the gate current value of a semiconductor device to the demanded largeness by a method wherein in addition to a regular current path to pass through P-N junction in a bulk, a by-pass gate current path according to a resistor layer is formed in parallel therewith to enlarge the apparent gate current, gate sensitivity is made as variable, and the resistance value of the resistor layer is controlled. CONSTITUTION:A selectively formed N type region 5 is formed in an island type in a P type region 4. In other words, P-N junction 9' is ended wholly at the main surface. The fine stripe type resistor layer 21 is formed in the type to make nearly a round of both a gate electrode 13 and a cathode electrode 14 between the under parts of both the electrodes 13, 14. The resistor layer 21 thereof is formed by implanting N-type impurities of phosphorus or antimony, for example, shallowly in the P type region 4 according to the ion implantation method. Or it can be formed by forming a polycrystalline silicon layer containing the prescribed concentration of phosphorus or antimony on the P type region 4. Moreover, as the resistor layer 21, the resistor layer connecting between the arbitrary two points under the gate electrode 13 and under the cathode electrode 14 is favorable.
摘要翻译：目的：通过以下方法控制半导体器件的栅极电流值达到所要求的大小：除了通过体积通过PN结的规则电流路径之外，形成根据电阻层的旁路栅极电流路径与此同时扩大视在栅极电流，使门灵敏度变为可变，并且控制电阻层的电阻值。构成：在P型区域4中以岛状形成选择性形成的N型区域5.换句话说，P-N结9'完全在主表面处结束。细条型电阻层21形成为在两个电极13,14的下部之间形成栅极电极13和阴极14的几乎一半的类型。其电阻层21通过将N 类型的磷或锑杂质，例如根据离子注入法在P型区域4中浅。或者可以通过在P型区域4上形成含有规定浓度的磷或锑的多晶硅层而形成。此外，作为电阻层21，连接在栅电极13下方的任意两点之间的电阻层，阴极14是有利的。

10. 发明专利

JP2014239327A 半導体装置の保護回路有权
标题翻译：保护半导体器件的电路
公开(公告)号：JP2014239327A
公开(公告)日：2014-12-18
申请号：JP2013120711
申请日：2013-06-07
申请人：株式会社デンソー , Denso Corp
发明人： KOYAMA KAZUHIRO
IPC分类号： H03K17/08 , H01L21/338 , H01L21/822 , H01L27/04 , H01L29/778 , H01L29/812
CPC分类号： H02H7/003 , H01L27/0248 , H01L29/7408 , H01L29/7412 , H01L29/778 , H03K17/08122
摘要：【課題】保護素子のサイズ増大を抑制しつつ、アバランシェエネルギー耐量を得ることができる半導体装置の保護回路を提供する。【解決手段】保護素子としてHEMT1のドレイン−ゲート間にサイリスタ2および第1抵抗3を備えると共に、HEMT1のソース−ゲート間に第2抵抗4およびダイオード5を備える。これにより、HEMT1のターンオフ時にサイリスタ2がオンして保護素子側に電流が流れるようにでき、そのときに第1抵抗3および第2抵抗4で分圧されて形成されるゲート電圧VgによってHEMT1をオンさせるられる。よって、ターンオフ時に、サイリスタ2の耐圧をクランプ電圧として、HEMT1に対してクランプ電圧を超える電圧が印加されないようにしつつ、HEMT1をオンすることで誘導性負荷に蓄積されたエネルギーを消費することが可能となる。【選択図】図1
摘要翻译：要解决的问题：提供一种用于保护产生雪崩能量容量的半导体器件的电路，同时抑制保护元件的尺寸增加。解决方案：作为保护元件，晶闸管2和第一电阻器3设置在漏极和漏极之间 HEMT 1的栅极和第二电阻器4和二极管5设置在HEMT 1的源极和栅极之间。当HEMT 1截止时，晶闸管2导通以允许电流流向保护元件和由第一电阻器3和第二电阻器4分压相应形成的栅极电压Vg可以使HEMT 1导通。在切断状态下，当晶闸管2的耐压为钳位电压时，防止超过钳位电压的电压被施加到HEMT 1上，可以调谐HEMT 1以消耗存储在感性负载。

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