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1. 发明专利

JPS61134066A Manufacture of gto thyristor 失效
标题翻译： GTO THYRISTOR的制造
公开(公告)号：JPS61134066A
公开(公告)日：1986-06-21
申请号：JP25668484
申请日：1984-12-05
申请人： Fuji Electric Co Ltd
发明人： WADA KAZUHISA
IPC分类号： H01L29/744
CPC分类号： H01L29/744
摘要： PURPOSE:To obtain the titled device of low ON-voltage and high effect of carrier suck-out by a method wherein an N-cathode layer is formed by phosphorus diffusion from one surface of the semiconductor substrate having PNP three layers, and a layer containing phosphorus in almost the same amount as that of the N-cathode layer is then formed on the surface of a P-anode layer; thereafter, Au diffusion is carried out. CONSTITUTION:After phosphorus diffusion to form the cathode layer, a phosphorus layer of low concentration is formed on the anode side. In other words, in a high vacuum, a thyristor wafer is turned to the anode side and placed on the electrode kept at a temperature of 200-300 deg.C, and voltage is impressed between the electrode opposed above the anode side. On Ar gas supply here, phosphorus decomposed by plasma effect mounts on the wafer, and phosphorus atoms penetrate into the wafer and deposit on the wafer surface. When the thyristor wafer is then subjected to Au diffusion e.g. at 870 deg.C for 90min, an Au distribution of less gradient than by the conventional method can be obtained. After Au diffusion, a required region of the N-cathode layer 24 is removed by selective etching, and the electrode is attached.
摘要翻译：目的：通过以下方法获得低导通电压和高载流子吸收效果的标题装置，其中通过从具有PNP三层的半导体衬底的一个表面的磷扩散形成N-阴极层，并且包含然后在P阳极层的表面上形成与N-阴极层几乎相同量的磷; 此后进行Au扩散。构成：在磷扩散形成阴极层后，在阳极侧形成低浓度的磷层。换句话说，在高真空中，将晶闸管晶片转向阳极侧并放置在保持在200-300℃温度的电极上，并且在阳极侧相对的电极之间施加电压。在这里的Ar气体供给中，通过等离子体效应分解的磷安装在晶片上，磷原子穿透晶片并沉积在晶片表面上。然后当晶闸管晶片经受Au扩散时，例如，在870℃下90分钟，可以获得比常规方法更小梯度的Au分布。在Au扩散之后，通过选择性蚀刻去除N-阴极层24的所需区域，并且连接电极。

2. 发明专利

JPS60138950A ELECTRODE CONNECTING CONDUCTOR FOR SEMICONDUCTOR ELEMENT 失效
公开(公告)号：JPS60138950A
公开(公告)日：1985-07-23
申请号：JP24712383
申请日：1983-12-27
申请人： FUJI ELECTRIC CO LTD
发明人： WADA KAZUHISA
IPC分类号： H01L21/60 , H01L23/49
摘要： PURPOSE:To prevent the titled electrode connecting conductor from shifting from the face of an electrode by rotating at the fixing time to a semiconductor chip for performing an assembling by a method wherein the electrode connecting conductor consists of a cylindrical part and a band-shaped part and the band-shaped part is formed of a shoulder part spreading to the axial direction of the cylindrical part, an end part which makes a vertical surface to the axis of the cylindrical part and a curving part interposing between the cylindrical part and the end part. CONSTITUTION:A part of a silver wire or a silver clad copper wire is flatly performed a processing using a press, etc. As a result, a cylindrical part 1 and a flat part 4 are effected. Then, the cylindrical part 1 and the flat part 4 are cut at positions shown by chain lines 5 and 6. After this, a bend processing is performed using an adapted mold. As a result, a shoulder part 7, a curving part 2 and an end part 3 which forms a vertical surface to the axis of the cylindrical part 1 are respectively completed. The working process is quite the same as that of the conventional electrode connecting conductor and the different points between both are only the cutting positions and the bending molds. So long as the shoulder part 7 is 1.5-3mm. in length, that will do. It is not necessary to lengthen more longer than the length. The electrode connecting conductor formed in such a method can be prevented from rotating at the assembling time by inserting the overhang 8 of the shoulder part 7 in the corresponding groove provided in the assembling jig.

3. 发明专利

JPS6088472A INSULATED GATE TYPE FET 失效
公开(公告)号：JPS6088472A
公开(公告)日：1985-05-18
申请号：JP19647283
申请日：1983-10-20
申请人： FUJI ELECTRIC CO LTD
发明人： WADA KAZUHISA
IPC分类号： H01L29/78
摘要： PURPOSE:To enlarge the range of the linearity between the drain voltage VDS and the drain current ID by a method wherein a semiconductor layer having P and N regions transiting in the directions of both the source and drain regions is provided on the surfaces in these regions via oxide film, and a gate electrode is provided thereon via oxide film. CONSTITUTION:An oxide film 14 of a thickness about 1/2 or less of the thickness of the conventional gate oxide film is formed, and the P-region 11 a semiconductor layer is formed on the source electrode side, and the N-region 12 a semiconductor layer on the drain region side thereon. Further thereon, an oxide film 24 about 1/2 of the conventional gate oxide films is formed, and the gate electrode 5 is adhered thereon. Since the junction potential Vbi of the transit region between the regions 11 and 12 is present in natural state, a P-channel 6 is already present; when a gate voltage VGS is impressed, a steped channel is formed. Impressing of the drain voltage VDS in this state produces pinch-off in a large region because the channel has a stepwise difference. As a result, the range of the linearity between the VDS and ID enlarges.

4. 发明专利

JPS59208758A Semiconductor element for complex semiconductor device 失效
标题翻译：复合半导体器件的半导体元件
公开(公告)号：JPS59208758A
公开(公告)日：1984-11-27
申请号：JP8334483
申请日：1983-05-12
申请人： Fuji Electric Co Ltd
发明人： WADA KAZUHISA
IPC分类号： H01L25/07 , H01L23/04 , H01L23/051 , H01L23/28 , H01L23/29 , H01L23/31 , H01L25/18
CPC分类号： H01L23/051 , H01L23/3157 , H01L23/3171 , H01L2224/48463 , H01L2924/10157 , H01L2924/10158 , H01L2924/1301 , H01L2924/00
摘要： PURPOSE:To obtain the titled element free of chip damage and deterioration of characteristics by a method wherein, when glass passivation is applied to the bevel-shaped side surfaces of a thyristor chip and the glass parts are protected by polyimide resin, outside ends of electrode plates, fixed to the front and the back surfaces of the chip, are extended outward and the glass parts are positioned inside the extended parts and these extended parts are filled with the resin. CONSTITUTION:The side surfaces of a thyristor chip 1 are bevel-shaped and glass passivation 7 is applied to these bevel-shaped side surfaces. Electrode plates 23 and 24, made of Mo, W or the like, are attached to the front and the back surfaces of the chip 1. An aperture is drilled in one of the electrode plates 23 and a lead wire 6 is connected to the exposed surface of the chip 1. In this composition, the parts of the electrode plates 23 and 24, attached to the chip 1, are protruded and the electrode ends of both sides of them are extended. Then the spaces surrounded by the extended parts are filled with polyimide resin 30 to cover the passivation parts 7 completely.
摘要翻译：目的：为了获得没有芯片损坏的标题元素和特性劣化的方法，其中当玻璃钝化被施加到晶闸管芯片的斜面侧表面并且玻璃部分被聚酰亚胺树脂保护时，电极的外端固定到芯片的前表面和后表面的板向外延伸，并且玻璃部件位于延伸部分内部，并且这些延伸部分被树脂填充。构成：晶闸管芯片1的侧面为斜边状，玻璃钝化物7被施加到这些斜边形的侧面。由Mo，W等制成的电极板23和24附接到芯片1的前表面和后表面。在一个电极板23中钻出孔，并且引线6连接到暴露的芯片1的表面。在该组成中，安装在芯片1上的电极板23和24的部分突出，并且其两侧的电极端部延伸。然后由延伸部分包围的空间填充有聚酰亚胺树脂30，以完全覆盖钝化部分7。

5. 发明专利

JPS5967636A Manufacture of mesa type semiconductor element 失效
标题翻译： MESA型半导体元件的制造
公开(公告)号：JPS5967636A
公开(公告)日：1984-04-17
申请号：JP17872682
申请日：1982-10-12
申请人： Fuji Electric Co Ltd
发明人： WADA KAZUHISA
IPC分类号： H01L21/306
CPC分类号： H01L21/306
摘要： PURPOSE:To prevent the cracking of a semiconductor while adjusting a mesa shape by fast sticking the other surface of the semiconductor, to a predetermined region of one surface thereof a protective layer is formed, on a metallic plate, coating the side surface of the semiconductor with an etching-resisting material and dipping the semiconductor in an etching liquid. CONSTITUTION:A protective pattern 2 is formed to the upper surface of a semiconductor board 1, and the semiconductor board 1 is pasted on the metallic plate 10 with pitch 12 so that the side surface section 9 and fringe section 11 of the semiconductor board 1 are coated completely. The metallic plate 10 resists the etching liquid, and a stainless steel plate is used for it. The semiconductor board 1 is not cracked in an etching process because it is reinforced mechanically by the metallic plate 10, and end sections are not changed into accute angles because the side surface of the semiconductor is protected completely with pitch 12. Variance is reduced in the shape of an etching groove because the temperature of the semiconductor board 1 is kept constant in surfaces by the thermal conduction of the metallic plate 10.
摘要翻译：目的：为了通过将半导体的另一个表面快速粘贴到半导体的另一个表面来调节台面形状来防止半导体的破裂，在其一个表面的预定区域上形成保护层，在金属板上涂覆半导体的侧表面用耐蚀刻材料并将半导体浸入蚀刻液中。构成：在半导体基板1的上表面形成保护图案2，将半导体基板1以间距12贴合在金属板10上，使得半导体基板1的侧面部9和边缘部11成为涂完全。金属板10抵抗蚀刻液，使用不锈钢板。由于半导体板1的侧表面被间距12完全保护，所以半导体板1由于金属板10机械加强而不会被破坏，并且由于半导体的侧表面完全被间距12保护，所以端部不会变成倾斜角。由于通过金属板10的热传导使半导体板1的温度保持恒定，所以蚀刻槽的形状。

6. 发明专利

JPS5936967A Reverse conduction thyristor 失效
标题翻译：反向导管THYRISTOR
公开(公告)号：JPS5936967A
公开(公告)日：1984-02-29
申请号：JP14733082
申请日：1982-08-25
申请人： Fuji Electric Co Ltd
发明人： WADA KAZUHISA
IPC分类号： H01L29/74
CPC分类号： H01L29/7416
摘要： PURPOSE:To improve the reverse conduction and switching characteristics by a method wherein difference is formed betweeen the resistivities of a diode part and a thyristor part at the time of the resistance adjustment for silicon as the base material by neutron irradiation method. CONSTITUTION:A reverse conduction thyristor is constituted by integrating the thyristor part 2 composed of a P-N-P-N layer and the diode part 1 composed of a P-N layer in reverse parallel in a piece of Si plate. In the thyristor composed in this manner, the resistivites of an N-layer 3 forming the base layer of the thyristor part 2 and an N-layer 4 of the diode part 1 are so formed as to be different by neutron irradiation. In other words, first the Si plate is so irradiated uniformly as to be provided with resistivity required for a diode. Next, only the thyristor part 2 is irradiated with thermal neutron, resulting in adjustment for the resistivity required for a thyristor.
摘要翻译：目的：通过中子辐照法对于硅作为基底材料的电阻调节时的二极管部分和晶闸管部分的电阻率之间形成差异的方法来提高反向传导和开关特性。构成：通过将由P-N-P-N层构成的晶闸管部分2和由P-N层构成的二极管部分1反向平行地集成在一块Si板中来构成反向导通晶闸管。在以这种方式构成的晶闸管中，形成晶闸管部分2的基极层的N层3和二极管部分1的N层4的电阻率被形成为不同于中子照射。换句话说，首先将Si板均匀地照射，以提供二极管所需的电阻。接下来，只有晶闸管部分2被热中子照射，从而调节晶闸管所需的电阻率。

7. 发明专利

JPS58192372A Manufacture of reverse conducting thyristor 失效
标题翻译：反向导管器的制造
公开(公告)号：JPS58192372A
公开(公告)日：1983-11-09
申请号：JP7570082
申请日：1982-05-06
申请人： Fuji Electric Co Ltd
发明人： WADA KAZUHISA
IPC分类号： H01L21/322 , H01L29/74
CPC分类号： H01L29/7416
摘要： PURPOSE:To reduce the forward voltage and the leakage current generating at the diode part of the titled thyristor by a method wherein, in the case of the thyristor wherein a thyristor and a diode are integrated in antiparallel form, thermal diffusion of P is performed at first and then lifetime killer is introduced thereon when an N layer, which constitutes a diode part, is formed. CONSTITUTION:An N type Si substrate 1 is deposited on a support plate 2, having the coefficient of thermal expansion for Mo or W or the like similar to Si, through the intermediary of an Al layer 3, one part thereof is used for thyristor part I and the other part is used for diode part II. According to this constitution, a P type region is provided on the lower side of the substrate 1 of the thyristor part I , an N type layer, having 10 /cm or thereabout of surface impurity density, is formed on the diode part II adjoining to the P type region, and the lifetime killer consisting of Au is implanted on the N type layer by performing an ion implantation. Subsequently, a P type layer is deposited on the whole surface, and the prescribed region is formed by diffusion in said P type layer.
摘要翻译：目的：通过以下方法降低在标称晶闸管的二极管部分产生的正向电压和漏电流，其中在晶闸管和二极管以反向平行形式集成的晶闸管的情况下，P的热扩散在当形成构成二极管部分的N +层时，首先引入终身杀伤剂。构成：将N型Si衬底1沉积在支撑板2上，其具有与Si类似的Mo或W等的热膨胀系数，通过Al 3层，其一部分用于晶闸管部分我和另一部分用于二极管第二部分。根据该结构，在晶闸管部件I的基板1的下侧设置P +型区域，具有10/20 / cm 2或其表面的N +型层杂质浓度形成在与P +型区域相邻的二极管部分II上，并且通过进行离子注入将由Au组成的寿命抑制剂注入N +型层。随后，在整个表面上沉积P型层，并且在所述P型层中通过扩散形成规定的区域。

8. 发明专利

JPS5374885A CENTER GATE TYPE THYRISTOR 失效
公开(公告)号：JPS5374885A
公开(公告)日：1978-07-03
申请号：JP15131476
申请日：1976-12-15
申请人： FUJI ELECTRIC CO LTD
发明人： WADA KAZUHISA
IPC分类号： H01L29/74 , H01L29/08
摘要： PURPOSE:To ensure a uniform gate ignition sensitivity as well as to increase the effective emitter area ratio, by giving a concentric arrangment with the emitter terminal only to the first row of the emitter short hole approaching the gate and outside the second row.

9. 发明专利

JPH0370908B2 失效
公开(公告)号：JPH0370908B2
公开(公告)日：1991-11-11
申请号：JP20920784
申请日：1984-10-05
申请人： FUJI ELECTRIC CO LTD
发明人： WADA KAZUHISA
IPC分类号： H01L29/47 , H01L29/872

10. 发明专利

JPS6366063B2 失效
公开(公告)号：JPS6366063B2
公开(公告)日：1988-12-19
申请号：JP8334483
申请日：1983-05-12
申请人： FUJI ELECTRIC CO LTD
发明人： WADA KAZUHISA
IPC分类号： H01L25/07 , H01L23/04 , H01L23/051 , H01L23/28 , H01L23/29 , H01L23/31 , H01L25/18

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