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1. 发明专利

JP2013515365A Power semiconductor devices 有权
公开(公告)号：JP2013515365A
公开(公告)日：2013-05-02
申请号：JP2012545222
申请日：2010-12-14
申请人：アーベーベー・テヒノロギー・アーゲー
发明人：ラヒモ、ムナフ
IPC分类号： H01L29/74 , H01L29/744
CPC分类号： H01L29/74 , H01L29/0839 , H01L29/102 , H01L29/744
摘要：４層ｎｐｎｐ構造、カソード面１１およびアノード面１２があり、ゲート電極４を介してターンオフできるパワー半導体デバイス１。カソード電極２とアノード電極３との間に以下の順で複数の層が配置される。 −外側縁によって囲まれ、中央領域がある第１導電型カソード層５、カソード層５はカソード電極２と直接の電気的コンタクトにある，−第２導電型ベース層６，−カソード層５よりも低いドーピング濃度を有する第１導電型ドリフト層７、アノード電極３と電気的コンタクトにある第２導電型アノード層８。ゲート電極４は、カソード面１１上にカソード電極２の横に配置され、ベース層６と電気的コンタクトにある。ベース層６は、カソード層５の中央領域に接触している、連続的な層としての、第１の深さに最大ドーピング濃度がある少なくとも１つの第１の層６１を具備する。第１の層６１よりも高いドーピング濃度を有し、第１の層６１とカソード層５との間に配置され、第１の層６１のほうを向いているカソード層５の外側縁をカバーする第２導電型抵抗減少層１０，１０'，１０''、この中でカソード層５の外側縁とベース層６との間の接合での抵抗が低減される。
【選択図】図３

2. 发明专利

JP2008277353A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2008277353A
公开(公告)日：2008-11-13
申请号：JP2007116158
申请日：2007-04-25
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NODA MASAAKI , OTA TOMONARI
IPC分类号： H01L29/861 , H01L29/06
CPC分类号： H01L29/8611 , H01L29/0619 , H01L29/0638 , H01L29/0692 , H01L29/0878 , H01L29/102 , H01L29/36 , H01L29/7395 , H01L29/74 , H01L29/7802
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing a chip size without changing characteristics such as on resistance and a breakdown voltage. SOLUTION: The semiconductor device comprises: a cathode layer 3 made of an n-type impurity region; and an anode layer 1 made of a p-type impurity region provided at the upper portion of the cathode layer 3. A plurality of floating ring layers 2 provided separately from the anode layer 1 and made of an electrically floating p-type impurity region are provided on the main surface of the cathode layer 3. Then, a well layer 4 made of an n-type impurity region including the floating ring layers 2 is provided. The well layer 4 can be, for example, provided individually to the floating ring layers 2. In this case, respective well layers 4 may be formed separately or overlappingly. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供能够在不改变诸如导通电阻和击穿电压的特性的情况下减小芯片尺寸的半导体器件。解决方案：半导体器件包括：由n型杂质区构成的阴极层3; 以及设置在阴极层3的上部的由p型杂质区构成的阳极层1.与阳极层1分开设置并由电浮置p型杂质区域构成的多个浮环层2是设置在阴极层3的主表面上。然后，设置由包括浮环2的n型杂质区构成的阱层4。阱层4可以例如分别设置在浮环2上。在这种情况下，可以分别或重叠地形成各个阱层4。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JPS6122474B2 JPS6122474B2 - 失效
公开(公告)号：JPS6122474B2
公开(公告)日：1986-05-31
申请号：JP13137677
申请日：1977-11-01
申请人： Erekutoritsuku Pawaa Risaachi Inst Inc
发明人： UIKUTAA EI KEI TEMUPURU
IPC分类号： H01L29/06 , H01L29/10 , H01L29/74
CPC分类号： H01L29/0688 , H01L29/0619 , H01L29/0661 , H01L29/102 , H01L29/7424
摘要： Self-protection against breakover turn-on failure is achieved for a thyristor by providing for adjustment of the curvature of the planar junction termination in the gate region. In addition, breakdown of the outer edge of the device at the junctions is maintained at a relatively higher breakdown voltage by the techniques of beveling, floating field rings or by etching around the cathode emitter region.

4. 发明专利

JPS61100966A Turn off type power semiconductor element and manufacture thereof 失效
标题翻译：关闭型电源半导体元件及其制造
公开(公告)号：JPS61100966A
公开(公告)日：1986-05-19
申请号：JP23146285
申请日：1985-10-18
申请人： Bbc Brown Boveri & Cie
发明人： BURUUNO BUROIHI , IENSU GOBUREHITO , PEETAA ROGUBUIRAA , YAN FUOOBORIRU
IPC分类号： H01L29/74 , H01L29/06 , H01L29/10 , H01L29/739 , H01L29/744 , H01L29/749
CPC分类号： H01L29/0661 , H01L29/102 , H01L29/7392 , H01L29/744 , H01L2224/48463 , H01L2224/72

5. 发明专利

JPS6190463A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS6190463A
公开(公告)日：1986-05-08
申请号：JP21136084
申请日：1984-10-11
申请人： Hitachi Haramachi Semiconductor Ltd , Hitachi Ltd
发明人： ONO MASAFUMI , SAKURADA SHUROKU , SAKAGAMI TADASHI , TAKATSUCHI SHIGEYASU
IPC分类号： H01L29/70 , H01L21/31 , H01L21/33 , H01L29/10 , H01L29/423 , H01L29/74
CPC分类号： H01L29/42308 , H01L29/102
摘要： PURPOSE:To enable excellent ON-OFF control by deforming the main electrode without contact with adjacent layers, by a method wherein the main surface of a semiconductor substrate at the part except the main electrode and the control electrode is coated with a surface stabilization film, and an insulation film is provided from the control electrode to the surface stabilization film. CONSTITUTION:A P-base layer 32 of the upper main surface is etched down in two steps and thus provided with high impurity concentration regions P 36. Each strip region 31 is provided with an aluminum cathode electrode 37, the lower step of the P-base layer 32 with an aluminum gate electrode 38, and the lower main surface with an anode electrode 39 made mainly of aluminum. The gate electrode 38 is in the form of surrounding each strip region 31. The remnant part of the upper main surface provided with the cathode electrode 37 and the gate electrode 38 is covered with an Si oxide film 40, and PIQ film 41 is provided from the gate electrode 38 to the Si oxide film 40 at the middle step. Therefore, even if the cathode electrode 37 deforms and elongates along the main surface in a lateral direction, it does not come into contact with the P-base layer 32.
摘要翻译：目的：为了通过使主电极变形而不与相邻层接触来实现优异的ON-OFF控制，通过其中除了主电极和控制电极之外的部分处的半导体衬底的主表面涂覆有表面稳定膜的方法，并且从控制电极到表面稳定膜设置绝缘膜。构成：上主表面的P基层32分两段蚀刻，由此设置有高杂质浓度区域P + 36。每个带状区域31设置有铝阴极电极37，下部步骤为具有铝栅电极38的P基层32和主要由铝制成的具有阳极电极39的下主表面。栅电极38是围绕每个条带31的形式。设置有阴极电极37和栅电极38的上主表面的残余部分被Si氧化物膜40覆盖，并且PIQ膜41由在中间阶段将栅电极38连接到Si氧化物膜40。因此，即使阴极电极37沿主表面沿横向变形和伸长，也不与P基层32接触。

6. 发明专利

JPS57121276A Gate turn-off thyristor 失效
标题翻译：门关闭三通阀
公开(公告)号：JPS57121276A
公开(公告)日：1982-07-28
申请号：JP664181
申请日：1981-01-20
申请人： Meidensha Electric Mfg Co Ltd
发明人： SUZUKI TOSHIAKI , SUEOKA TETSUO
IPC分类号： H01L29/744 , H01L29/10 , H01L29/74
CPC分类号： H01L29/102
摘要： PURPOSE:To suppress a commutation surge voltage of a gate turn-off thyristor by the breakdown between a cathode N2 layer and a high resistance layer by forming a low resistance buried layer and the high resistance layer in the P2 base layer of the gate turn off (GTO) thyristor of four layers P1, N1, P2, N2. CONSTITUTION:A low resistance buried P2 type layer is formed in a lattice shape in the P2 base layer of a GTO thyristor having four layers of P1, N1, P2, N2, and a high resistance P2 layer is formed between the low resistance bufied layer and a cathode N2 layer. The impurity density of the high resistance layer and the distance between the low resistance buried layer and the cathode N2 layer are determined to the prescribed value so that the breakdown voltage between the N2P2 layers becmes the vicinity of the offset power voltage, thereby suppressing the commutation surge voltage by the breakdown. Thus, the protecting function can be enhanced without providing special over voltage suppressing circuit.
摘要翻译：目的：通过形成低电阻掩埋层，通过栅极的P2基极层中的高电阻层截止，通过阴极N2层和高电阻层之间的击穿来抑制栅极截止晶闸管的换向浪涌电压关断（GTO）晶闸管，四层P1，N1，P2，N2。构成：在具有四层P1，N1，P2，N2的GTO晶闸管的P2基层中，栅电极形成低电阻埋层P2 ++层，高电阻P2 < 形成在低阻抗层和阴极N2层之间。将高电阻层的杂质浓度和低电阻掩埋层和阴极N2层之间的距离确定为规定值，使得N2P2层之间的击穿电压由于偏移电源电压的附近，从而通过击穿来抑制换向浪涌电压。因此，可以在不设置特殊的过电压抑制电路的情况下增强保护功能。

7. 发明专利

JPS5734366A Thyristor 失效
标题翻译： THYRISTOR
公开(公告)号：JPS5734366A
公开(公告)日：1982-02-24
申请号：JP11050980
申请日：1980-08-09
申请人： Mitsubishi Electric Corp
发明人： TAKEDA MITSUYOSHI
IPC分类号： H01L29/74 , H01L29/10
CPC分类号： H01L29/102
摘要： PURPOSE:To improve the gate sensitivity of the subject thyristor without reducing dV/dt resistant strength by a method wherein, in the case of a three-terminal element having four-layer structure, an n layer (or a p layer) is provided, aparting from an emitter layer, on the p base layer (or an n base layer) on which a gate electrode will be provided. CONSTITUTION:For example, in the case of a four-layer thyristor consisting of a pE layer, an nB layer, a pB layer and an nE layer, an nO layer 5 is formed in the pB layer 2 simultaneously with the diffusion performed on the nE layer 4, for example, and the nO layer and the pB layer are short-circuited by an electrode G. In this structure, when the gate voltage having the gate G as positive and a cathode as negative is applied, a junction 13 is biased inversely and the gate current reaches the nE layer 4 through the route as shown by solid arrow lines, thereby enabling to increase the implanting efficiency and increase the gate sensitivity. On the other hand, the dV/dt resistant strength is not reduced even when the nO layer is provided, because the direction of the displacement current ingredient shown by the dotted lines has no relation with the existence of the nO layer 5. Accordingly, a thyristor which is suited to a high-sensitive and low current capacity element having a low gate trigger current can be obtained.
摘要翻译：目的：为了提高目标晶闸管的门灵敏度，而不降低dV / dt抗性强度，其中在具有四层结构的三端元件的情况下，提供n层（或ap层），分开来自发射极层，在其上将设置栅电极的p基极层（或n基极层）上。构成：例如，在由pE层，nB层，pB层和nE层构成的四层晶闸管的情况下，在pB层2中同时形成nO层5， nE层4，并且nO层和pB层被电极G短路。在该结构中，当施加栅极G为正极且阴极为阴极的栅极电压时，结13为反向偏置，栅极电流通过实线箭头线所示的路径到达nE层4，从而能够增加植入效率并增加栅极灵敏度。另一方面，由于虚线所示的位移电流成分的方向与nO层5的存在无关，因此即使设置nO层，dV / dt电阻强度也不会降低。因此，可以获得适合具有低栅极触发电流的高灵敏度和低电流容量元件的晶闸管。

8. 发明专利

JP5328930B2 Semiconductor devices and related methods having a current shift area 有权
公开(公告)号：JP5328930B2
公开(公告)日：2013-10-30
申请号：JP2011538639
申请日：2009-11-20
申请人：クリーインコーポレイテッドCree Inc.
发明人：チャン、キンチュン , アガルワル、アナント、ケイ．
IPC分类号： H01L21/331 , H01L21/8222 , H01L27/082 , H01L29/732 , H01L29/74 , H01L29/744 , H01L29/861 , H01L29/868
CPC分类号： H01L29/66068 , H01L29/0619 , H01L29/0657 , H01L29/0661 , H01L29/0692 , H01L29/1004 , H01L29/102 , H01L29/1608 , H01L29/73 , H01L29/744
摘要： A semiconductor device may include a semiconductor buffer layer having a first conductivity type and a semiconductor mesa having the first conductivity type on a surface of the buffer layer. In addition, a current shifting region having a second conductivity type may be provided adjacent a corner between the semiconductor mesa and the semiconductor buffer layer, and the first and second conductivity types may be different conductivity types. Related methods are also discussed.

9. 发明专利

JP3581447B2 High-voltage semiconductor device 失效
公开(公告)号：JP3581447B2
公开(公告)日：2004-10-27
申请号：JP21352395
申请日：1995-08-22
申请人：三菱電機株式会社
发明人：肇秋山
IPC分类号： H01L21/336 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/73 , H01L29/739 , H01L29/74 , H01L29/745 , H01L29/78 , H01L29/786
CPC分类号： H01L29/7824 , H01L29/0615 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/1008 , H01L29/102 , H01L29/1083 , H01L29/402 , H01L29/41725 , H01L29/66674 , H01L29/7302 , H01L29/7393 , H01L29/7394 , H01L29/7436 , H01L29/7455 , H01L29/7801 , H01L29/7835
摘要： An n - layer (2) is formed on a main surface of a p-type semiconductor substrate (1). A p - diffusion region (5) is formed at a surface of n - layer (2). A p diffusion region (6) is formed contiguous to one end of p - diffusion region (5). A plurality of p diffusion regions (20) containing p-type impurity the concentration of which is higher than that of p - diffusion region (5) are formed in p - diffusion region (5). A p diffusion region (3) is formed such that it is spaced apart from p - diffusion region (5). A gate electrode (9) is formed on a surface of n - layer (2) positioned between p diffusion region (3) and p - diffusion region (5) with an oxide film (10) interposed. A drain electrode (12) is formed in contact with a surface of p diffusion region (6). Furthermore, an n diffusion region (4) is formed adjacent to p diffusion region (3), and a source electrode (11) is formed in contact with both a surface of n diffusion region (4) and a surface p diffusion region (3).

10. 发明专利

JPS6110276A Manufacture of semiconductor element 失效
标题翻译：半导体元件的制造
公开(公告)号：JPS6110276A
公开(公告)日：1986-01-17
申请号：JP13163384
申请日：1984-06-26
申请人： Meidensha Electric Mfg Co Ltd
发明人： HAYASHI YASUHIDE
IPC分类号： H01L29/74 , H01L29/10 , H01L29/744
CPC分类号： H01L29/102
摘要： PURPOSE:To contrive the reduction in number of the manufacturing process and the improvement of manufacturing yield by a method wherein a buffer layer that covers crystal defects generating in a gate layer channel is formed collectively with the gate layer by diffusing impurities through a thin oxide film in order to form the former layer in manufacture of a semiconductor element having a buried gate. CONSTITUTION:After formation of an oxide film, the window of the part corresponding to patterns of a P2 layer and a P2 buffer layer is bored in a P1N1P2 structure by a photo resist process. Next, a thinner oxide film than the oxide film formed in the former process is formed by reoxidation. Then, the window of the part corresponding to the P2 layer pattern is bored by a photo resist process, and the P2 buffer layer and the P2 layer are formed at the same time by selective diffusion of boron with the patterns of the two layers. Since the P2 buffer layer is formed by boron diffusion through a thin oxide film in such a manner, one time boron diffusion is sufficient.
摘要翻译：目的：通过以下方法来制造制造工艺数量的减少和制造成品率的提高，其中通过将杂质扩散通过薄氧化膜而将覆盖在栅极层通道中产生的晶体缺陷的缓冲层与栅极层一体地形成以便在具有掩埋栅极的半导体元件的制造中形成前一层。构成：在形成氧化膜之后，通过光致抗蚀剂工艺在P1N1P2结构中对与P2 ++层和P2 +缓冲层的图案相对应的部分的窗口进行钻孔。接下来，通过再氧化形成比在前一工艺中形成的氧化膜更薄的氧化膜。然后，通过光刻胶工艺对与P2 <++>层图案对应的部分的窗口进行钻孔，并且通过选择性扩散同时形成P2 +缓冲层和P2 ++层的硼与两层的图案。由于通过以这种方式通过薄氧化膜的硼扩散形成P2 +缓冲层，所以一次硼扩散就足够了。

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