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2. 发明专利

JP2011066459A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2011066459A
公开(公告)日：2011-03-31
申请号：JP2010293608
申请日：2010-12-28
申请人： Panasonic Corp , パナソニック株式会社
发明人： TAKEMURA YASUSHI , HIRANO HIROSHIGE , TAKAHASHI MASAO , SANO HIKARI , ITO YUTAKA , KOIKE KOJI
IPC分类号： H01L21/3205 , H01L21/82 , H01L23/52
CPC分类号： H01L2224/05093 , H01L2224/05095
摘要： PROBLEM TO BE SOLVED: To attain a high-reliabilty semiconductor device which protects an element from a stress generated by a bonding process and a probing process and which does not generate cracks on an insulating film at the lower side of a bonding pad. SOLUTION: The semiconductor device is equipped with a semiconductor substrate, a first interlayer insulating film 3 formed on the semiconductor substrate, a pad 1 formed on the first interlayer insulating film 3 and a plurality of first wirings 12, formed independently in the first interlayer insulating film 3 with mutual interval therebetween in a region immediately below the pad 1. The plurality of first wirings 12 are provided in a region immediately below the pad 1, with a plurality of first direction wirings 12A extending in a first direction and a plurality of second direction wirings 12B that extends in a second direction orthogonal to the first direction. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了获得保护元件免受接合过程和探测过程产生的应力的高可靠性半导体器件，并且不会在焊盘的下侧的绝缘膜上产生裂纹。解决方案：半导体器件配备有半导体衬底，形成在半导体衬底上的第一层间绝缘膜3，形成在第一层间绝缘膜3上的焊盘1和多个第一布线12，第一层间绝缘膜3在垫1的正下方的区域中相互间隔开。多个第一布线12设置在焊盘1正下方的区域中，多个第一方向布线12A沿第一方向延伸，并且多个第二方向布线12B，其沿与第一方向正交的第二方向延伸。版权所有（C）2011，JPO＆INPIT

3. 发明专利

JPWO2007074530A1 半導体装置とその製造方法有权
公开(公告)号：JPWO2007074530A1
公开(公告)日：2009-06-04
申请号：JP2007551842
申请日：2005-12-27
申请人：富士通株式会社
发明人：永井　孝一 , 孝一永井
IPC分类号： H01L21/3205 , H01L21/8246 , H01L23/52 , H01L27/10 , H01L27/105
CPC分类号： H01L27/11507 , H01L21/76826 , H01L21/76832 , H01L21/76834 , H01L23/53295 , H01L24/05 , H01L27/11509 , H01L2224/02166 , H01L2224/04042 , H01L2224/05093 , H01L2224/05094 , H01L2224/05095 , H01L2224/05554 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01059 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/05042 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2924/3025 , H01L2924/00
摘要：耐湿性を向上したパッドを備えた半導体装置を提供する。半導体装置は、半導体基板に形成された複数の半導体素子を含む回路部と、回路部を覆って、半導体基板上に形成された絶縁積層と、絶縁積層中に形成され、配線パターンとビア導電体とを含む多層配線構造と、半導体基板上方に形成され、多層配線構造に接続されたパッド電極構造を含み、パッド電極構造は、複数層のパッド用配線パターンと、パッド用配線パターン間を接続するパッド用ビア導電体を含み、少なくとも最上層のパッド用配線パターンはパッドパターンと、その外側をループ状に取り囲むシールパターンを含み、他のパッド用配線パターンの少なくとも1つは連続した、シールパターンに対応する大きさの拡大パッドパターンを有し、パッド用ビア導電体は、パッドパターンに対応して配置された複数の柱状ビア導電体とシールパターンに対応して配置されたループ状壁部とを含む。

4. 发明专利

JP2009105160A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2009105160A
公开(公告)日：2009-05-14
申请号：JP2007274216
申请日：2007-10-22
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： ISHII YASUYUKI
IPC分类号： H01L21/768 , H01L21/3205 , H01L21/60 , H01L21/66 , H01L23/52 , H01L23/522
CPC分类号： H01L24/06 , H01L23/5226 , H01L24/03 , H01L24/05 , H01L2224/02166 , H01L2224/05093 , H01L2224/05095 , H01L2224/05552 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/0603 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/04941 , H01L2924/04953 , H01L2924/1306 , H01L2924/14 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To suppress enlargement of a chip size in a semiconductor device. SOLUTION: The semiconductor device includes circuit Vias 7 which are formed in an interlayer insulating film 6 between upper and lower wiring layers 5 and connect them, flat ring-like protection Vias 9 which are installed in the interlayer insulating film 6 below an electrode pad 4 and either of which is connected to the electrode pad 4, a protection wiring layer 10 constituted of the wiring layers 5 connected to the other protection Via 9, and a semiconductor element arranged on a main face of the semiconductor substrate below the protection wiring layer 10. A lower part of the electrode pad 4 whose surface is exposed is surrounded with the protection Via 9 and the protection wiring layer 10. Width (x) of the protection Via 9 is not less than width (y) of the circuit Via 7. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：抑制半导体器件中的芯片尺寸的放大。解决方案：半导体器件包括电路通路7，其形成在上布线层5和下布线层5之间的层间绝缘膜6中，并将它们连接，安装在层间绝缘膜6中的平环状保护通孔9 电极焊盘4，并且其中任一个连接到电极焊盘4，由与另一个保护电极9连接的布线层5构成的保护布线层10以及设置在半导体衬底的主面下面的保护层的半导体元件其表面露出的电极焊盘4的下部被保护通孔9和保护布线层10围绕。保护通孔9的宽度（x）不小于电路的宽度（y）通过7.版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2007150150A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2007150150A
公开(公告)日：2007-06-14
申请号：JP2005345347
申请日：2005-11-30
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： HAYASHI TAKAHIRO , TOYOSHIMA SHUNSUKE , SAKAMOTO KAZUO , MORINO NAOZUMI , TANAKA KAZUO
IPC分类号： H01L21/822 , H01L21/3205 , H01L21/82 , H01L23/52 , H01L27/04
CPC分类号： H01L23/49844 , H01L23/49811 , H01L23/50 , H01L23/5226 , H01L23/5286 , H01L23/53228 , H01L23/585 , H01L24/05 , H01L24/06 , H01L24/49 , H01L27/0255 , H01L27/092 , H01L2224/02166 , H01L2224/05025 , H01L2224/05093 , H01L2224/05095 , H01L2224/05124 , H01L2224/05624 , H01L2224/06102 , H01L2224/06133 , H01L2224/06143 , H01L2224/06153 , H01L2224/06163 , H01L2224/49105 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/12036 , H01L2924/1306 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： PROBLEM TO BE SOLVED: To provide a technology capable of reducing a semiconductor device in size (plane size) regarding a technology applied to the semiconductor device, especially, a semiconductor device having bonding pads. SOLUTION: In the semiconductor device; an input/output circuit 11 is formed on a semiconductor substrate 30, a ground wiring 7 and power supply line 8 pass over it, furthermore, and a conductor layer 51 used for bonding pad 4 is formed on it. Further, the input/output circuit 11 is formed by MISFET elements of nMISFET forming region 21 and pMISFET forming region 27, resistive elements of resistive element forming regions 22, 26 functioning as a protection element, and diode elements of diode element forming regions 23, 25. An interconnection 53, connected to these protection elements, of lower layer than the ground wiring 7 and the power supply line 8 is connected to a conductor layer 51, in such a way that it is drawn out at a location between the nMISFET forming region 21 and the pMISFET forming region 27, and at a drawing region 24 between the ground wiring 7 and the power supply line 8. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够减小半导体器件的尺寸（平面尺寸）的技术，涉及应用于半导体器件的技术，特别是具有接合焊盘的半导体器件。
解决方案：在半导体器件中; 此外，在半导体衬底30，接地布线7和电源线8上形成输入/输出电路11，并且在其上形成用于焊盘4的导体层51。此外，输入/输出电路11由nMISFET形成区域21和pMISFET形成区域27的MISFET元件，用作保护元件的电阻元件形成区域22,26的电阻元件和二极管元件形成区域23的二极管元件形成，连接到这些保护元件的，比接地布线7和电源线8下层的互连53连接到导体层51，使得它在nMISFET形成之间的位置被拉出区域21和pMISFET形成区域27以及接地布线7和电源线8之间的绘制区域24。（C）2007，JPO＆INPIT

6. 发明专利

JP3898350B2 Semiconductor device 有权
公开(公告)号：JP3898350B2
公开(公告)日：2007-03-28
申请号：JP22334298
申请日：1998-08-06
申请人：富士通株式会社
发明人：隆博加藤
IPC分类号： H01L21/60 , H01L23/52 , H01L21/3205 , H01L23/12 , H01L23/485
CPC分类号： H01L24/05 , H01L24/06 , H01L24/48 , H01L2224/04042 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05554 , H01L2224/05556 , H01L2224/05557 , H01L2224/05599 , H01L2224/4807 , H01L2224/48453 , H01L2224/48463 , H01L2224/49171 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/14 , H01L2224/45099 , H01L2924/00 , H01L2224/85399
摘要： A semiconductor device includes a semiconductor chip and a wiring formed on the chip. An interlayer film is located on the wiring. A pad is located on the interlayer film and is connected to the wiring with contacts that extend from the wiring, through the interlayer film, to the pad. The contacts include a first group of contacts located near the perimeter of the pad and a second group of pads located near the center of the pad. By limiting the number and placement of the contacts, the pad allows for a secure connection between the pad and the wiring and between the pad and a bonding wire.

7. 发明专利

JP2007067332A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2007067332A
公开(公告)日：2007-03-15
申请号：JP2005254852
申请日：2005-09-02
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： TAKEMURA YASUSHI , HIRANO HIROSHIGE , TAKAHASHI MASAO , SANO HIKARI , ITO YUTAKA , KOIKE KOJI
IPC分类号： H01L21/3205 , H01L21/82 , H01L23/52
CPC分类号： H01L24/05 , H01L22/32 , H01L2224/02166 , H01L2224/04042 , H01L2224/05093 , H01L2224/05094 , H01L2224/05095 , H01L2224/05553 , H01L2224/05554 , H01L2224/05556 , H01L2224/05624 , H01L2224/48463 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01033 , H01L2924/01057 , H01L2924/01074 , H01L2924/01079 , H01L2924/3025 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device for which an element is protected from stress generated by a bonding process and a probing process without generating a crack on an insulating film on the lower side of a bonding pad.
SOLUTION: The semiconductor device comprises a pad 1, and a first interlayer insulating film 3 and a second interlayer insulating film 4 which are formed under the pad 1 and in which wiring is embedded. In the first interlayer insulating film 3 and the second interlayer insulating film 4, two or more lines of first wiring 12 and two or more lines of second wiring 13 are respectively embedded. Each first wiring 12 is a planar rectangular conductive film formed on the lower side of the pad 1 at an interval from each other. On the lower side of the pad 1, each first wiring 12 is straightly formed and does not have a bend or a branch. Also, on the lower side of the pad 1, the first interlayer insulating film 3 is not provided with wiring for electrically connecting the first wiring 12 with each other.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种高可靠性的半导体器件，其元件被保护免受由接合工艺和探测过程产生的应力，而不会在焊盘的下侧的绝缘膜上产生裂纹。解决方案：半导体器件包括衬垫1和形成在焊盘1下面并且嵌入布线的第一层间绝缘膜3和第二层间绝缘膜4。在第一层间绝缘膜3和第二层间绝缘膜4中，分别嵌入两条或更多条第一布线12和两条或更多条第二布线13。每个第一布线12是以相互间隔形成在垫1的下侧的平面矩形导电膜。在焊盘1的下侧，每个第一布线12被直线地形成并且不具有弯曲或分支。此外，在焊盘1的下侧，第一层间绝缘膜3不具有用于将第一布线12彼此电连接的布线。版权所有（C）2007，JPO＆INPIT

8. 发明专利

JP2007019538A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2007019538A
公开(公告)日：2007-01-25
申请号：JP2006254166
申请日：2006-09-20
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KATO TAKAHIRO
IPC分类号： H01L21/60 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522
CPC分类号： H01L24/05 , H01L2224/04042 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05554 , H01L2224/05557 , H01L2224/48 , H01L2224/4807 , H01L2224/48247 , H01L2224/4845 , H01L2224/48463 , H01L2224/49171 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2924/00014 , H01L2924/00 , H01L2224/05556 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device increasing bonding strength between pads and a wire, while having a strong structure against stress acting on the pads. SOLUTION: An interconnect line formed on a chip is connected with pads 3a to 3d arranged on the both sides of an interlayer film that are joined with a bonding wire 6 through contacts 9. The contacts 9 are densely arranged in the periphery and center section of the pads 3a to 3d. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种提高焊盘和焊丝之间的接合强度的半导体器件，同时具有抵抗作用在焊盘上的应力的强结构。解决方案：芯片上形成的互连线与布置在层间膜两侧的焊盘3a至3d连接，该层间膜通过触点9与接合线6接合。触点9密集地布置在外围，焊盘3a至3d的中心部分。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2006237607A Pad arrangement and its pad structure in semiconductor device 审中-公开
标题翻译：半导体器件中的PAD布置及其PAD结构
公开(公告)号：JP2006237607A
公开(公告)日：2006-09-07
申请号：JP2006043891
申请日：2006-02-21
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIM NA-RAE , SON TAISHOKU , OH HEE JOONG , KWAK BYUNG-HEON , SHU ZAIKUN , KIM HYUN DON , CHO EIMIN
IPC分类号： H01L21/66 , H01L21/3205 , H01L21/82 , H01L21/822 , H01L23/52 , H01L27/04 , H01L27/10
CPC分类号： H01L24/03 , H01L22/32 , H01L24/05 , H01L24/06 , H01L2224/04042 , H01L2224/05093 , H01L2224/05094 , H01L2224/05095 , H01L2224/05552 , H01L2224/05553 , H01L2224/0603 , H01L2224/45144 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01046 , H01L2924/01068 , H01L2924/01079 , H01L2924/01082 , H01L2924/13091 , H01L2924/19041 , H01L2224/48 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a pad arrangement structure and its arranging method in a semiconductor device which can reduce region in which the pad shall be formed. SOLUTION: In a pad arrangement structure, which is formed on the semiconductor device, used for an operation test of the semiconductor device or wire bonding, the structure is formed so that a size of at least one pad not processed in the wire bonding may be smaller than a size of at least one pad processed in the wire bonding on the semiconductor device. COPYRIGHT: (C)2006,JPO&NCIPI

10. 发明专利

JP2006216840A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2006216840A
公开(公告)日：2006-08-17
申请号：JP2005029142
申请日：2005-02-04
申请人： Fujitsu Ltd , 富士通株式会社
发明人： WATANABE TAKAKUNI , KOYASHIKI TAKESHI , OZAWA HIROYUKI , MIMURA TOMOAKI
IPC分类号： H01L27/04 , H01L21/3205 , H01L21/768 , H01L21/82 , H01L21/822 , H01L23/52
CPC分类号： H01L24/06 , H01L23/5286 , H01L24/05 , H01L2224/05093 , H01L2224/05095 , H01L2224/05553 , H01L2224/05624 , H01L2224/05647 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/14 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To sufficiently feed current from the external to a power-supply ring of a semiconductor device, even though the widths of its pads are made narrow. SOLUTION: The semiconductor device has pads constituted in a plurality of wiring layers 11-14, 15A and has a power-supply ring R1 formed in the shape of a ring and for feeding a power supply to its inner circuit which is fed via its pads for the power supply. Its pads for the power supply and the power-supply ring are connected by its vias VIA provided respectively on the upper and lower sides of the power-supply ring. Consequently, its disposable vias for connecting thereby its pads for the power supply and the power-supply ring are so made at least twice as many as the conventional ones as to increase the current quantity to fed to the power-supply ring, even though the widths of its pads are made narrow. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：即使其焊盘的宽度窄，也能够从外部向半导体器件的电源环充分供给电流。解决方案：半导体器件具有构造在多个布线层11-14,15A中的焊盘，并且具有形成为环形形状的电源环R1，并且用于将电源馈送到其馈送的内部电路通过其电源垫。其电源和电源环的焊盘通过分别设置在电源环的上侧和下侧的通孔VIA连接。因此，其用于连接其用于电源和电源环的焊盘的一次性通孔被制成是常规电极的至少两倍，以增加供给电源环的电流量，即使其垫的宽度变窄。版权所有（C）2006，JPO＆NCIPI

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