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1. 发明专利

JP2007150150A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2007150150A
公开(公告)日：2007-06-14
申请号：JP2005345347
申请日：2005-11-30
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： HAYASHI TAKAHIRO , TOYOSHIMA SHUNSUKE , SAKAMOTO KAZUO , MORINO NAOZUMI , TANAKA KAZUO
IPC分类号： H01L21/822 , H01L21/3205 , H01L21/82 , H01L23/52 , H01L27/04
CPC分类号： H01L23/49844 , H01L23/49811 , H01L23/50 , H01L23/5226 , H01L23/5286 , H01L23/53228 , H01L23/585 , H01L24/05 , H01L24/06 , H01L24/49 , H01L27/0255 , H01L27/092 , H01L2224/02166 , H01L2224/05025 , H01L2224/05093 , H01L2224/05095 , H01L2224/05124 , H01L2224/05624 , H01L2224/06102 , H01L2224/06133 , H01L2224/06143 , H01L2224/06153 , H01L2224/06163 , H01L2224/49105 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/12036 , H01L2924/1306 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： PROBLEM TO BE SOLVED: To provide a technology capable of reducing a semiconductor device in size (plane size) regarding a technology applied to the semiconductor device, especially, a semiconductor device having bonding pads. SOLUTION: In the semiconductor device; an input/output circuit 11 is formed on a semiconductor substrate 30, a ground wiring 7 and power supply line 8 pass over it, furthermore, and a conductor layer 51 used for bonding pad 4 is formed on it. Further, the input/output circuit 11 is formed by MISFET elements of nMISFET forming region 21 and pMISFET forming region 27, resistive elements of resistive element forming regions 22, 26 functioning as a protection element, and diode elements of diode element forming regions 23, 25. An interconnection 53, connected to these protection elements, of lower layer than the ground wiring 7 and the power supply line 8 is connected to a conductor layer 51, in such a way that it is drawn out at a location between the nMISFET forming region 21 and the pMISFET forming region 27, and at a drawing region 24 between the ground wiring 7 and the power supply line 8. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够减小半导体器件的尺寸（平面尺寸）的技术，涉及应用于半导体器件的技术，特别是具有接合焊盘的半导体器件。
解决方案：在半导体器件中; 此外，在半导体衬底30，接地布线7和电源线8上形成输入/输出电路11，并且在其上形成用于焊盘4的导体层51。此外，输入/输出电路11由nMISFET形成区域21和pMISFET形成区域27的MISFET元件，用作保护元件的电阻元件形成区域22,26的电阻元件和二极管元件形成区域23的二极管元件形成，连接到这些保护元件的，比接地布线7和电源线8下层的互连53连接到导体层51，使得它在nMISFET形成之间的位置被拉出区域21和pMISFET形成区域27以及接地布线7和电源线8之间的绘制区域24。（C）2007，JPO＆INPIT

2. 发明专利

JP2008192971A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2008192971A
公开(公告)日：2008-08-21
申请号：JP2007027965
申请日：2007-02-07
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： MORINO NAOZUMI , SAKAMOTO KAZUO , TSUTSUMI YASUSHI
IPC分类号： H01L25/065 , H01L21/60 , H01L25/07 , H01L25/18
CPC分类号： H01L24/06 , H01L24/05 , H01L2224/02166 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/0603 , H01L2224/32145 , H01L2224/45 , H01L2224/45015 , H01L2224/45144 , H01L2224/48 , H01L2224/48095 , H01L2224/48145 , H01L2224/48227 , H01L2224/48465 , H01L2224/48479 , H01L2224/4848 , H01L2224/48624 , H01L2224/49 , H01L2224/4903 , H01L2224/49051 , H01L2224/49171 , H01L2224/49175 , H01L2224/49433 , H01L2224/85051 , H01L2225/06562 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/20752 , H01L2924/00 , H01L2224/48471 , H01L2924/00012 , H01L2224/4554
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device for achieving high integration and high reliability in simple configurations. SOLUTION: A first semiconductor chip having a plurality of first pads are loaded on the surface of a loaded substrate having a plurality of leads on the surface and a second semiconductor chip having a plurality of second and third pads is loaded on the loaded substrate or the first semiconductor chip. The plurality of leads are connected through first bonding wire to the plurality of corresponding first pads. The plurality of second pads are connected through second bonding wire to the plurality of corresponding first pads. The plurality of third pads are connected through third bonding wire to the plurality of corresponding leads. The first and second bonding wires have thickness which is thicker than that of the third bonding wire, and the first and second pads have areas larger than that of the third pad. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种在简单配置中实现高集成度和高可靠性的半导体器件。解决方案：具有多个第一焊盘的第一半导体芯片被装载在具有多个引线的表面上的已加载衬底的表面上，并且具有多个第二和第三焊盘的第二半导体芯片被加载到加载衬底或第一半导体芯片。多个引线通过第一接合线连接到多个对应的第一焊盘。多个第二焊盘通过第二接合线连接到多个对应的第一焊盘。多个第三焊盘通过第三接合线连接到多个相应的引线。第一和第二接合线具有比第三接合线更厚的厚度，并且第一和第二焊盘的面积大于第三焊盘的面积。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2004355163A Data processor, and electronic apparatus 审中-公开
标题翻译：数据处理器和电子设备
公开(公告)号：JP2004355163A
公开(公告)日：2004-12-16
申请号：JP2003150031
申请日：2003-05-28
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： SAKAMOTO KAZUO , MORINO NAOZUMI , KUDO IKUO
IPC分类号： G06K17/00 , G06F1/04 , G06F1/10 , G06F3/06 , G06F5/06 , G06F15/78
CPC分类号： G06F5/06 , G06F1/10
摘要： PROBLEM TO BE SOLVED: To provide a microcomputer having a memory card interface to correctly fetch data when a card such as an MMC card is connected. SOLUTION: The microcomputer includes the interface (221) with an outer device such as the memory card (100). The interface includes an output driver (DRV) which is connected to an outer terminal (241) for outputting a clock signal, so as to output the clock signal; and an equivalence load circuit (257) for imparting delay which is equivalent to the delay due to the outer load of connection to the outer terminal, to the clock signal taken out from the arbitrary position of a clock signal route in the preceding stage of the output driver, in order to generate the clock signal for fetching data inputted from the memory card. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有存储卡接口的微型计算机，以在连接诸如MMC卡的卡时正确地取出数据。解决方案：微型计算机包括具有诸如存储卡（100）的外部装置的接口（221）。接口包括连接到外部端子（241）的输出驱动器（DRV），用于输出时钟信号，以输出时钟信号; 以及等效负载电路（257），用于将与外部端子的外部负载相关的延迟等效于从前一级的时钟信号路由的任意位置取出的时钟信号输出驱动器，以产生用于取出从存储卡输入的数据的时钟信号。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2008028274A Manufacturing method for semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2008028274A
公开(公告)日：2008-02-07
申请号：JP2006201413
申请日：2006-07-25
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： SAKAMOTO KAZUO , TANAKA KAZUO , MORINO NAOZUMI
IPC分类号： H01L21/66 , H01L21/3205 , H01L21/822 , H01L23/52 , H01L27/04
CPC分类号： H01L24/06 , H01L2224/05553 , H01L2224/06179 , H01L2924/14 , H01L2924/181 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a technique for easily determining a leak current that is caused by a crack formed on an insulating film underneath electrode pads. SOLUTION: A probe is put simultaneously to a signal electrode pad 2, and an inspection electrode pad 3 which is an isolated pattern formed on a corner of a semiconductor chip, to measure a leak current between the inspection electrode pad 3 and a circle-around power interconnect 7 that runs underneath a plurality of signal electrode pads 2 and the inspection electrode 3 via insulating films 4 and 6. If a leak current larger than a rating current is measured between the inspection electrode pad 3 and the circle-around power interconnect 7, a leak current is measured between the inspection electrode pad 3 and the signal electrode pad 2 (2A) adjacent thereto. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于容易地确定由在电极焊盘下方的绝缘膜上形成的裂纹引起的漏电流的技术。解决方案：将探头同时放置到信号电极焊盘2和形成在半导体芯片的拐角上的隔离图案的检查电极焊盘3，以测量检查电极焊盘3和检测电极焊盘3之间的漏电流。通过绝缘膜4和6在多个信号电极焊盘2和检查电极3之下运行的环绕电源互连7。如果在检查电极焊盘3和环绕周围之间测量大于额定电流的泄漏电流功率互连7，在检查电极焊盘3和与其相邻的信号电极焊盘2（2A）之间测量泄漏电流。版权所有（C）2008，JPO＆INPIT

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