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1. 发明专利

JP2007019538A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2007019538A
公开(公告)日：2007-01-25
申请号：JP2006254166
申请日：2006-09-20
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KATO TAKAHIRO
IPC分类号： H01L21/60 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522
CPC分类号： H01L24/05 , H01L2224/04042 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05554 , H01L2224/05557 , H01L2224/48 , H01L2224/4807 , H01L2224/48247 , H01L2224/4845 , H01L2224/48463 , H01L2224/49171 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2924/00014 , H01L2924/00 , H01L2224/05556 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device increasing bonding strength between pads and a wire, while having a strong structure against stress acting on the pads. SOLUTION: An interconnect line formed on a chip is connected with pads 3a to 3d arranged on the both sides of an interlayer film that are joined with a bonding wire 6 through contacts 9. The contacts 9 are densely arranged in the periphery and center section of the pads 3a to 3d. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种提高焊盘和焊丝之间的接合强度的半导体器件，同时具有抵抗作用在焊盘上的应力的强结构。解决方案：芯片上形成的互连线与布置在层间膜两侧的焊盘3a至3d连接，该层间膜通过触点9与接合线6接合。触点9密集地布置在外围，焊盘3a至3d的中心部分。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JPH10187520A FILE UPDATE PROCESSING METHOD 失效
公开(公告)号：JPH10187520A
公开(公告)日：1998-07-21
申请号：JP29418097
申请日：1997-10-27
申请人： FUJITSU LTD
发明人： KATO TAKAHIRO , KIJIMA HIROSHI
IPC分类号： G06F12/00 , G06F13/00 , G06F15/16
摘要： PROBLEM TO BE SOLVED: To conform an updating process for a file group on a slave server side to that of a master server by updating files on the other information processor according to an updating process kind based upon logging data. SOLUTION: Log data based upon the update of a data base 14 on the master server 1 are stacked at a log stacking process part 11 and adjusted at a log editing process part 12 as to repeated or duplicate update data, etc., and then the data are sent from a communication part 13 and received by a communication part 23 of the slave server 2; and a data base update part 21 updates the data base S24 according to the log data. At this time, a file which is already updated is obtained by accessing the data base M14 on the master server as to some file whose update is specified with the log data to update the data base S24 on the slave server 2, and a file whose deletion is specified is processed directly in the data base S24 on the slave server 2.

3. 发明专利

JPH04259116A MULTI-INPUT NAND CIRCUIT 失效
公开(公告)号：JPH04259116A
公开(公告)日：1992-09-14
申请号：JP2119191
申请日：1991-02-14
申请人： FUJITSU LTD , FUJITSU VLSI LTD
发明人： KATO TAKAHIRO , HACHIGA MORIHIKO
IPC分类号： H03K19/003 , H03K19/0948 , H03K19/20
摘要： PURPOSE:To eliminate a change in an operating speed depending on the input state to each terminal Tin by connecting a Pch transistor (TR) TRp and an Nch TRm to each input terminal Tin in an uniform. state. CONSTITUTION:Sources of PchFETs 11-13 are connected to a power supply VCC, three-stages of NchFETs 11-13 each are connected between a drain and ground and groups 1a-1c are connected together. Gates of the TRs 11-13 are connected to gates of TRs 14,17,20. One of upper, middle and lower stages of the TR groups 1a-1c is selected and connected to each input terminal Tin1-Tin3 as specified. Thus, the condition to each of the input terminals Tin1-Tin3 in the 3-input NAND circuit is uniform, and even when the input signals Vin1, Vin2 are at an H level and the input signal Vin3 changes from L to H level, and even when the input signals Vin2, Vin3 are at an H level and the input signal Vin1 changes from L to H level, the leading speed of an output signal- Vout is equal and no skew is caused.1.

4. 发明专利

JPH0346254A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH0346254A
公开(公告)日：1991-02-27
申请号：JP18056789
申请日：1989-07-14
申请人： FUJITSU LTD , FUJITSU VLSI LTD
发明人： KATO TAKAHIRO
IPC分类号： H01L21/822 , H01L21/82 , H01L27/04 , H01L27/118
摘要： PURPOSE:To enable a required chip to be supplied at a low cost in a short time through a wiring process by a method wherein a base current control means is provided in the buffer circuit of a gate array. CONSTITUTION:A base current control means is provided to enable a output drive transistor Q1 of each buffer circuit to change in drive capacity corresponding to various requirements of users, where the base current control means is formed and arranged in such a manner that an impurity diffusion layer 2 of the substrate of a MOS transistor is divided into two pieces 2-1 and 2-2 of optional length in the direction in which gates 3a and 3b are arranged. Outer parts A and D and outer parts B and C of the diffusion layers 2-1 and 2-2 are selected to serve as a source 4, and when an Al wiring is provided, for instance, to the source 4 concerned, predeterminate source parts are optionally combined as selected to be connected, whereby a channel can be changed in area, so that an amplification factor beta is made to change and consequently an output current can be also changed. By this setup, a gate array type semiconductor integrated circuit with a drive output required by a user can be easily obtained in a short time.

5. 发明专利

JP2000058583A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2000058583A
公开(公告)日：2000-02-25
申请号：JP22334298
申请日：1998-08-06
申请人： FUJITSU LTD , FUJITSU VLSI LTD
发明人： KATO TAKAHIRO
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/60 , H01L23/12 , H01L23/485
摘要： PROBLEM TO BE SOLVED: To enable to increase the bonding strength between a pad and a wire while ensuring a construction which is resistant to the stress acting on the pad. SOLUTION: A wiring layer 8 formed on a chip and a pad 3 to which a bonding wire 6 is joined and which is disposed on the wiring layer 8 through an interlayer film 7 are connected through contacts 9. Contacts 9 are formed on the periphery of the pad 3. A number of contacts 9 corresponding to the area in which the wire 6 is joined are formed in the center of the pad 3.

6. 发明专利

JPH04196814A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH04196814A
公开(公告)日：1992-07-16
申请号：JP32753590
申请日：1990-11-28
申请人： FUJITSU LTD , FUJITSU VLSI LTD
发明人： KATO TAKAHIRO
IPC分类号： H03K19/018
摘要： PURPOSE:To suppress the deterioration of an operating speed, and to output an ECL level signal after converting it into a TTL level signal by connecting the collector of the first transistor with the base of a transistor for a pull-up, and connecting the collector of the second transistor with the base of a transistor for a pull-down. CONSTITUTION:The collector of a first transistor Tr1 is connected with the base of a transistor Tr4 for the pull-up, that is, the transistor Tr 4 at the previous stage of a transistor Tr5, and the collector of a second transistor Tr2 is connected with the base of a transistor Tr6 for the pull-down. Then, an output signal Vout in the TLL level which operates an almost full swing between a power source Vcc and a ground G, is outputted from an output terminal Tout, based on the change of an input signal Vin in the ECL level, and the output transistors Tr4-Tr6 which output an output signal in the TTL level are directly driven by the transistors Tr1 and Tr2 to which the input signal Vin in the ECL level is inputted. Thus, the deterioration of the operating speed can be suppressed, and the ECL level signal can be outputted after converting it into the TTL, level signal.

7. 发明专利

JPS62257747A SCHMITT CIRCUIT FOR SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS62257747A
公开(公告)日：1987-11-10
申请号：JP10011586
申请日：1986-04-30
申请人： FUJITSU LTD
发明人： KATO TAKAHIRO , HIROCHI KATSUJI , SUGIHARA TAKANORI
IPC分类号： H01L27/118 , H01L21/82 , H01L21/822 , H01L27/04 , H03K3/2893 , H03K5/01
摘要： PURPOSE:To vary the threshold voltage of each of a rise and a fall by mounting a plurality of electrodes to each of resistors for supplying the collector currents of each of two transistors, selecting an arbitrary electrode and connecting a wiring. CONSTITUTION:A P-type region 13 is formed in an N-type element formation region 10 on a P-type substrate. The region 13 constitutes resistors RB, RC for supplying the collector currents of transistors TrQ2, Q3 organizing a Schmitt circuit, and electrodes 14a-14e are shaped. The electrode 14a in these electrodes is connected to a power terminal. The electrode 14b or 14c is connected to a collector for the TrQ3, the constant of the resistor RC is reduced when the electrode 14b is connected, and the constant of the resistor RC is increased when the electrode 14c is connected. The electrode 14d or 14c is connected similarly to a collector for the TrQ2. Accordingly, the electrodes 14a, 14c and the electrodes 14b, 14d are selected, thus varying the threshold voltage of each of the rise and fall of the Schmitt circuit.

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