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1. 发明专利

JP5138319B2 Memory system and said operating method. 有权
公开(公告)号：JP5138319B2
公开(公告)日：2013-02-06
申请号：JP2007231833
申请日：2007-09-06
申请人：三星電子株式会社Samsung Electronics Co.,Ltd.
发明人：李▲キョング▼翰 , 崔永準 , 李洋燮
IPC分类号： G06F12/16
CPC分类号： G06F11/1068 , G11C16/04 , G11C29/76 , G11C2029/0409 , G11C2029/0411 , G11C2229/723
摘要： A method for operating a memory system including a flash memory device having a plurality of memory blocks includes determining whether a read error generated during a read operation of the flash memory device is caused by read disturbance and replacing a memory block which includes the read error, with a spare memory block if the read error is caused by read disturbance.

2. 发明专利

JP2006031873A Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：JP2006031873A
公开(公告)日：2006-02-02
申请号：JP2004211330
申请日：2004-07-20
申请人： Toshiba Corp , 株式会社東芝
发明人： KAWAI KOICHI
IPC分类号： G11C29/04 , G11C16/06
CPC分类号： G11C29/848 , G11C16/04 , G11C29/802 , G11C29/82 , G11C29/835 , G11C2229/723
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory employing a defective column replacement system which enables chip area reduction. SOLUTION: The semiconductor memory is provided with: a memory cell array in which electrically rewritable nonvolatile memory cells are arrayed; a sense amplifier circuit for reading the data of the memory cell array; a first data holding circuit for holding data indicating good or bad of each column of the memory cell array; and a second data holding circuit for holding data read from the first data holding circuit to control the skipping of a defective column address based on the output thereof. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种使用能够减少芯片面积的缺陷色谱柱更换系统的半导体存储器。解决方案：半导体存储器设置有：存储单元阵列，其中排列电可重写非易失性存储器单元; 用于读取存储单元阵列的数据的读出放大器电路; 第一数据保持电路，用于保存指示存储单元阵列的每列的好坏的数据; 以及第二数据保持电路，用于保持从第一数据保持电路读取的数据，以根据其输出来控制有缺陷的列地址的跳过。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2004234052A Storage device 有权
公开(公告)号：JP2004234052A
公开(公告)日：2004-08-19
申请号：JP2003018296
申请日：2003-01-28
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： SHIBUYA HIROFUMI , HARA IKUO , GOTO HIROYUKI , SHIODA SHIGEMASA
IPC分类号： G06F12/16 , G06F3/06 , G06F12/00 , G06K17/00 , G11C29/00 , H02H3/05
CPC分类号： G06F11/1666 , G06F11/004 , G06F11/20 , G06F11/2053 , G11C16/04 , G11C29/44 , G11C29/4401 , G11C29/76 , G11C2029/0407 , G11C2029/0409 , G11C2229/723
摘要： PROBLEM TO BE SOLVED: To greatly improve reliability of a semiconductor memory by detecting, notifying and rescuing an abnormal area.
SOLUTION: Internal configuration of semiconductor memories 3
1 and 3
2 arranged in a memory card 1 is comprised of a user area, a substitute area, an area substitute information storage area, and a management area. Internal configuration of semiconductor memories 3
3 -3
5 is comprised of a user area, a substitute area, and a management area. The user area is a data area available to a user, and the substitute area is an area substitutable when a defect occurs in the user area. The area substitute information storage area stores area substitute information, while the management area stores the substitute information. An information processing part 2 executes substitution in two steps. In one step, area substitute processing is carried out in an idle time of a memory card 1 when a defect-prone action of an area is detected in the semiconductor memory. In the other step, the area substitute processing is instantly carried out when a defect action of the area is detected.
COPYRIGHT: (C)2004,JPO&NCIPI

4. 发明专利

JP4102338B2 Semiconductor memory device 有权
公开(公告)号：JP4102338B2
公开(公告)日：2008-06-18
申请号：JP2004211330
申请日：2004-07-20
申请人：株式会社東芝
发明人：鉱一河合
IPC分类号： G11C29/04 , G11C16/06
CPC分类号： G11C29/848 , G11C16/04 , G11C29/802 , G11C29/82 , G11C29/835 , G11C2229/723
摘要： A semiconductor memory device including: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a sense amplifier circuit configured to read data of the memory cell array; first data hold circuits configured to hold data for designating whether each column of the memory cell array is defective or not; and a second data hold circuit configured to hold data read out of the first dada hold circuits, and control to skip a defective column address of the memory cell array in accordance with the data read out of the first data hold circuit.

5. 发明专利

JP2008065830A Memory system and its operating method 有权
标题翻译：记忆系统及其操作方法
公开(公告)号：JP2008065830A
公开(公告)日：2008-03-21
申请号：JP2007231833
申请日：2007-09-06
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： LEE KYOONG-HAN , SAI EIJUN , LEE YANG-SUP
IPC分类号： G06F12/16
CPC分类号： G06F11/1068 , G11C16/04 , G11C29/76 , G11C2029/0409 , G11C2029/0411 , G11C2229/723
摘要： PROBLEM TO BE SOLVED: To provide a method of operating a memory system comprising a flash memory device with a plurality of memory blocks. SOLUTION: The operating method comprises a step of determining whether a read error caused during a read operation of the flash memory device is caused by a read disturb, and a step of replacing a memory block having the read error with an empty memory block when the read error is determined to be caused by the read disturb. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种操作包括具有多个存储器块的闪存器件的存储器系统的方法。解决方案：操作方法包括确定在闪速存储器件的读取操作期间引起的读取错误是否由读取干扰引起的步骤，以及将具有读取错误的存储器块替换为空的存储器的步骤当读取错误被确定为由读取干扰引起时，阻塞。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2007164839A Nonvolatile semiconductor memory device and its self-test method 有权
标题翻译：非线性半导体存储器件及其自检方法
公开(公告)号：JP2007164839A
公开(公告)日：2007-06-28
申请号：JP2005356447
申请日：2005-12-09
申请人： Toshiba Corp , 株式会社東芝
发明人： SAITO SAKATOSHI
IPC分类号： G11C29/12 , G01R31/28 , G11C29/44
CPC分类号： G11C16/0416 , G11C16/04 , G11C16/3459 , G11C29/16 , G11C29/44 , G11C29/48 , G11C29/765 , G11C2029/0409 , G11C2029/1208 , G11C2229/723
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device and its self-test method, in which a test time can be shortened.
SOLUTION: A test signal storing part 24A is constituted of erasable and writable storage means, and stores test information required for executing a test. A decoder 24B for BIST decodes a test command inputted to an interface 23 for BIST and selects test information stored in the test signal storage part 24A. A sense amplifier 18 reads out test information selected by the decoder 24B for BIST from the test signal storage part 24A, and a test signal register 19 holds the test information. A control circuit 14 controls test operation about whether main body memory cells 20A are operated normally or not based on the test information held in the test signal register 19. When the main body memory cells 20A are not operated normally, a defective block register 20C stores that the main body memory cells 20A are defective.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以缩短测试时间的非易失性半导体存储器件及其自检方法。解决方案：测试信号存储部分24A由可擦除和可写存储装置构成，并存储执行测试所需的测试信息。用于BIST的解码器24B对输入到BIST的接口23的测试命令进行解码，并选择存储在测试信号存储部分24A中的测试信息。读出放大器18从测试信号存储部分24A读取由解码器24B选择的用于BIST的测试信息，并且测试信号寄存器19保存测试信息。控制电路14基于保持在测试信号寄存器19中的测试信息来控制主体存储单元20A是否正常操作的测试操作。当主体存储单元20A不正常地操作时，缺陷块寄存器20C存储主体存储单元20A有缺陷。版权所有（C）2007，JPO＆INPIT

7. 发明专利

JP4828938B2 Non-volatile semiconductor memory device and a method of driving the same 有权
公开(公告)号：JP4828938B2
公开(公告)日：2011-11-30
申请号：JP2005378861
申请日：2005-12-28
申请人：株式会社東芝
发明人：拓也二山
IPC分类号： G11C16/02 , G11C16/06 , G11C29/04
CPC分类号： G11C8/10 , G11C16/04 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C29/765 , G11C29/82 , G11C29/832 , G11C2229/723

8. 发明专利

JP2011165249A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2011165249A
公开(公告)日：2011-08-25
申请号：JP2010025335
申请日：2010-02-08
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： ITO SHIN
IPC分类号： G11C29/44 , G06F12/16 , G11C16/02 , G11C16/04 , G11C17/00 , G11C29/56
CPC分类号： G11C29/765 , G11C29/56 , G11C29/883 , G11C2029/4402 , G11C2229/723
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can suppress an increase in time required for re-inspection. SOLUTION: The semiconductor device includes a plurality of main storage areas which store data, a first management area which corresponds to each main storage area, and stores defective block information which shows whether the main storage area is defective based on respective results of a first inspection which determines whether the main storage area is defective, and a second inspection which determines whether the main storage area performed after the first inspection is defective; and a second management area which corresponds to each main storage area and stores defective block information only based on the result of the first inspection. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够抑制再次检查所需的时间增加的半导体装置。解决方案：半导体器件包括存储数据的多个主存储区域，对应于每个主存储区域的第一管理区域，并且存储显示主存储区域是否有缺陷的缺陷块信息，其基于各个存储区域的相应结果确定主存储区域是否有缺陷的第一检查和确定在第一检查之后执行的主存储区域是否有缺陷的第二检查; 以及对应于每个主存储区域的第二管理区域，并且仅基于第一检查的结果来存储缺陷块信息。版权所有（C）2011，JPO＆INPIT

9. 发明专利

JP4425250B2 Semiconductor non-volatile memory 有权
公开(公告)号：JP4425250B2
公开(公告)日：2010-03-03
申请号：JP2006221479
申请日：2006-08-15
申请人： Okiセミコンダクタ株式会社
发明人：晃宏原田 , 伸一村田 , 博之谷川
IPC分类号： G11C16/02 , G11C16/06 , G11C29/04 , G11C29/12 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/10 , G06F11/1004 , G11C16/04 , G11C16/0475 , G11C29/02 , G11C29/027 , G11C29/028 , G11C29/42 , G11C29/72 , G11C2029/0407 , G11C2229/723
摘要： In a semiconductor nonvolatile memory, plural first nonvolatile memory cells are arranged in the memory array. Plural memory areas are arranged in the memory array and have plural second nonvolatile memory cells which store the same predetermined information. A sequence circuit generates a memory address, a latch selection signal, and a control signal at predetermined timings when a power is turned on. A write-read unit writes and reads information to and from the memory array and the memory areas based on the memory address and the control signal. A latch circuit latches the predetermined information, read by the write-read unit, based on the latch selection signal. A selection-drive unit selects the first or second nonvolatile memory cells based on the memory address and the predetermined information latched by the latch circuit, and applies a predetermined voltage to drive the selected first or second nonvolatile memory cells.

10. 发明专利

JP4686350B2 Non-volatile semiconductor memory device and a self-test method 有权
公开(公告)号：JP4686350B2
公开(公告)日：2011-05-25
申请号：JP2005356447
申请日：2005-12-09
申请人：株式会社東芝
发明人：栄俊斉藤
IPC分类号： G11C29/12 , G01R31/28 , G11C29/04 , G11C29/44
CPC分类号： G11C16/0416 , G11C16/04 , G11C16/3459 , G11C29/16 , G11C29/44 , G11C29/48 , G11C29/765 , G11C2029/0409 , G11C2029/1208 , G11C2229/723

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