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1. 发明专利

JP2014146220A Method for designing semiconductor device, program, and design device 有权
标题翻译：设计半导体器件，程序和设计器件的方法
公开(公告)号：JP2014146220A
公开(公告)日：2014-08-14
申请号：JP2013015030
申请日：2013-01-30
申请人： Fujitsu Semiconductor Ltd , 富士通セミコンダクター株式会社
发明人： ASANO KOSHO
IPC分类号： G06F17/50 , H01L21/82 , H01L21/822 , H01L27/04
CPC分类号： G06F17/5068 , G06F2217/62 , G06F2217/82
摘要： PROBLEM TO BE SOLVED: To suppress the occurrence of jitter constraint violation.SOLUTION: A method of designing a semiconductor device comprises the steps of: obtaining a relation between a distance from a back bias control unit 1 that controls the back bias of a transistor Tr and the amount of noise of a control signal that is output from the back bias control unit 1 (step S1); obtaining the amount of increase in jitter due to the amount of the noise on a clock path that is connected to a circuit section (IP macro) 2, on the basis of a relation between the back bias control unit 1 and the amount of noise (step S2); and arranging the circuit section 2 and clock path on the basis of the amount of increase in the jitter and an allowable value of the jitter in the circuit section 2 (step S3).
摘要翻译：要解决的问题：抑制抖动约束违规的发生。解决方案：设计半导体器件的方法包括以下步骤：获得控制晶体管Tr的背偏置的背偏压控制单元1的距离之间的关系和从背偏压控制单元1输出的控制信号的噪声量（步骤S1）; 基于背偏置控制单元1和噪声量之间的关系，获得由连接到电路部分（IP宏）2的时钟路径上的噪声量引起的抖动增加量步骤S2）; 并根据抖动的增加量和电路部分2中的抖动允许值（步骤S3），设置电路部分2和时钟路径。

2. 发明专利

JP5562394B2 Global clock handler object for Hdl environment 有权
公开(公告)号：JP5562394B2
公开(公告)日：2014-07-30
申请号：JP2012230294
申请日：2012-09-28
申请人：アップルインコーポレイテッド
发明人：ダブリューヤンウィリアム , アールフェルナンドシャメーラ
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/62

3. 发明专利

JP2010197291A Semiconductor device, design method and design device of the semiconductor device, and failure detection method 有权
标题翻译：半导体器件，半导体器件的设计方法和设计器件以及故障检测方法
公开(公告)号：JP2010197291A
公开(公告)日：2010-09-09
申请号：JP2009044095
申请日：2009-02-26
申请人： Panasonic Corp , パナソニック株式会社
发明人： FUJII NAOHIRO , OBI KINYA , YOSHIMURA SHINICHI
IPC分类号： G01R31/28 , H01L21/82 , H01L21/822 , H01L27/04
CPC分类号： G01R31/318552 , G06F17/5031 , G06F17/505 , G06F2217/14 , G06F2217/62 , G06F2217/84
摘要： PROBLEM TO BE SOLVED: To detect a bridge failure generated between clock signal wires of a semiconductor device.
SOLUTION: During a scan test or the like, scan paths 100a, 100b are constituted of a flip-flop circuit 101. During a normal operation, clock signals 104, 105 are supplied to each flip-flop circuit 101 by selection of a selector 102, and on the other hand, during the scan test, a scan clock signal 106 is supplied thereto through XOR circuits 200, 201. When, for example, control signals 202, 203 inputted from a failure detection device or the like of the semiconductor device are "L" (Low level), the XOR circuits 200, 201 output the scan clock signal 106 as it is. On the other hand, in the case of "H" (High level), the XOR circuits 200, 201 output an inverted scan clock signal acquired by inverting the scan clock signal 106 (shifting the phase as much as 180°).
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：检测在半导体器件的时钟信号线之间产生的桥接故障。解决方案：在扫描测试等期间，扫描路径100a，100b由触发器电路101构成。在正常操作期间，通过选择时钟信号104,105被提供给每个触发器电路101 选择器102，另一方面，在扫描测试期间，通过异或电路200,201向扫描时钟信号106提供扫描时钟信号106.例如，当从故障检测装置等输入的控制信号202,203 半导体器件为“L”（低电平），异或电路200,201原样输出扫描时钟信号106。另一方面，在“H”（高电平）的情况下，异或电路200,201输出通过反相扫描时钟信号106（相位多达180度）而获得的反相扫描时钟信号。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2010086284A Method for designing clock signal providing circuit, information processing apparatus, and program 有权
标题翻译：设计时钟信号提供电路，信息处理设备和程序的方法
公开(公告)号：JP2010086284A
公开(公告)日：2010-04-15
申请号：JP2008254634
申请日：2008-09-30
申请人： Fujitsu Ltd , 富士通株式会社
发明人： NEGISHI TATSUHIKO
IPC分类号： G06F17/50 , G06F1/10 , G06F1/12 , H03K5/15 , H03K19/00
CPC分类号： G06F17/5031 , G06F2217/62
摘要： PROBLEM TO BE SOLVED: To provide a configuration in which a clock line can be shortened all over a circuit, in providing a clock signal in a semiconductor integrated circuit. SOLUTION: A method for designing a clock signal providing circuit is made optimum for exchanging and moving circuit elements among groups of circuit elements, summing up a distance between a position of the circuit element and a central position for every group before and after execution, maintaining groups after execution when the summed up value of all the groups decreases, and maintaining the groups before execution when the value does not decrease. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供在半导体集成电路中提供时钟信号的时钟线可以在整个电路上被缩短的配置。解决方案：一种用于设计时钟信号提供电路的方法是最佳的，用于在电路元件组之间交换和移动电路元件，将电路元件的位置与每组前后的中心位置相加当所有组的总计值减少时，执行后维护组，并在该值不减少时，在执行之前维护组。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2009152451A Integrated circuit device and its layout designing method 审中-公开
标题翻译：集成电路设备及其布局设计方法
公开(公告)号：JP2009152451A
公开(公告)日：2009-07-09
申请号：JP2007330215
申请日：2007-12-21
申请人： Texas Instr Japan Ltd , 日本テキサス・インスツルメンツ株式会社
发明人： TOYONO YUTAKA , MIYAGI TOMOHIDE
IPC分类号： H01L21/822 , G06F17/50 , H01L21/82 , H01L27/04
CPC分类号： H01L27/0207 , G06F17/5068 , G06F2217/62
摘要： PROBLEM TO BE SOLVED: To provide an integrated circuit device capable of reducing electric power used for distribution of common signals such as a clock signal and capable of suppressing timing dispersion of common signals and its layout designing method.
SOLUTION: An ICG1 circuit layout area A1 is divided into a plurality of areas containing approximately the same number of ICG1, and one CTB5 (clock tree buffer at the end of a clock tree) is disposed in each divided area. The CTB5 in each divided area supplies a common clock signal to ICG1 in the disposed area. In this way, fan-outs of CTBs (CTB5) at the end of the clock tree are made approximately equal to each other, so that their drive loads are approximately equal. This structure can suppress the skew of clock signals in flip-flops very small, even when the number of CTBs is reduced greatly in comparison with a general clock tree synthesis by a general EDA tool.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供一种集成电路装置，其能够减少用于分配诸如时钟信号的公共信号的电力，并且能够抑制公共信号的定时分散及其布局设计方法。解决方案：ICG1电路布局区域A1被分成包含大致相同数量的ICG1的多个区域，并且在每个划分区域中设置一个CTB5（时钟树结束时钟树缓冲器）。每个划分区域中的CTB5在设置区域中向ICG1提供公共时钟信号。以这种方式，时钟树结尾处的CTB（CTB5）的扇出大致相等，使得它们的驱动负载大致相等。这种结构可以抑制触发器中的时钟信号的偏斜非常小，即使与通用EDA工具的通用时钟树合成相比，CTB的数量大大降低。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2009015851A Method and system for efficiently using multi-source network of control logic to achieve timing closure in clocked logic circuit 有权
标题翻译：方法和系统，有效地利用控制逻辑的多源网络实现时钟锁定电路中的时序关闭
公开(公告)号：JP2009015851A
公开(公告)日：2009-01-22
申请号：JP2008172903
申请日：2008-07-02
申请人： Internatl Business Mach Corp , インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation
发明人： JOHN M ISAKSON , ROSSER THOMAS EDWARD , KRISTEN M TUCKER , CURLEY LAWRENCE DAVID , METS ARJEN , POUARZ TRAVIS W
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/62
摘要： PROBLEM TO BE SOLVED: To provide a method, system, and computer program product, for achieving timing closure in a clocked logic circuit.
SOLUTION: For each local clock buffer in a set of local clock buffers, a logic synthesis tool determines a clock control signal input from a set of clock control signal inputs that will drive a clock control signal to the local clock buffer at a target frequency such that a first timing constraint may be met. The operation performed by the logic synthesis tool forms a determined clock control signal input. Responsive to the logic synthesis tool determining the determined clock control signal input, the logic synthesis tool couples the local clock buffer to the determined clock control signal input that drives the clock control signal to the local clock buffer at the target frequency to achieve timing closure in the clock driven logic circuit.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于在时钟逻辑电路中实现定时闭合的方法，系统和计算机程序产品。解决方案：对于一组本地时钟缓冲器中的每个本地时钟缓冲器，逻辑综合工具确定从一组时钟控制信号输入端输入的时钟控制信号，该时钟控制信号输入将在时钟控制信号输入端口将时钟控制信号驱动到本地时钟缓冲器目标频率使得可以满足第一定时约束。由逻辑综合工具执行的操作形成确定的时钟控制信号输入。响应于确定所确定的时钟控制信号输入的逻辑综合工具，逻辑综合工具将本地时钟缓冲器耦合到所确定的时钟控制信号输入端，该时钟控制信号输入以目标频率驱动时钟控制信号到本地时钟缓冲器，以实现定时闭合时钟驱动逻辑电路。版权所有（C）2009，JPO＆INPIT

7. 发明专利

JP2005284426A Asynchronous circuit verification method and asynchronous circuit verification program 有权
标题翻译：异步电路验证方法和异步电路验证程序
公开(公告)号：JP2005284426A
公开(公告)日：2005-10-13
申请号：JP2004094030
申请日：2004-03-29
申请人： Fujitsu Ltd , 富士通株式会社
发明人： IKEDA NORIYUKI , IWAMOTO MASAMI , KIKUCHI HIROE , IKEUCHI KENTARO , TSURUTA YOICHI , SONODA JUNJI , WATANABE ATSUSHI
IPC分类号： G06F17/50 , G06F1/10
CPC分类号： G06F17/5059 , G06F17/5018 , G06F2217/62 , G06F2217/84 , G06F2217/86
摘要： PROBLEM TO BE SOLVED: To efficiently and accurately perform the operation verification of an asynchronous circuit. SOLUTION: An asynchronous list 12 is generated by extracting all asynchronous parts from an RTL1 by an asynchronous extraction program 11, and a control task inserting part 20 generates a control card 21 for controlling a clock/delay control part 40 and inserts a control task inserted into the RTL1. In a logic simulation stage by a simulator 33 for an RTL 31 into which the control task is inserted, the clock/delay control part 40 is linked with the simulator 33, and a modulation clock or a delay signal is inserted into the control task of the RTL 31. Thus, various delay states are prepared in the logic simulation stage of the RTL31 prior to logic synthesis, and to accurately and efficiently perform the operation verification of the asynchronous circuit. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：有效和准确地执行异步电路的操作验证。解决方案：通过由异步提取程序11从RTL1提取所有异步部分来产生异步列表12，并且控制任务插入部分20生成用于控制时钟/延迟控制部分40的控制卡21，并插入控制任务插入RTL1。在由控制任务插入的RTL 31的仿真器33的逻辑仿真阶段中，时钟/延迟控制部分40与仿真器33相连，调制时钟或延迟信号被插入到因此，在逻辑合成之前，在RTL31的逻辑仿真阶段中准备了各种延迟状态，并准确而有效地执行异步电路的操作验证。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP6089728B2 半導体装置の設計方法、プログラム及び設計装置有权
标题翻译：设计半导体装置，程序和设计装置的方法
公开(公告)号：JP6089728B2
公开(公告)日：2017-03-08
申请号：JP2013015030
申请日：2013-01-30
申请人：株式会社ソシオネクスト
发明人：浅野宏昇
IPC分类号： H01L21/82 , H01L21/822 , H01L27/04 , G06F17/50
CPC分类号： G06F17/5068 , G06F2217/62 , G06F2217/82

9. 发明专利

JP2014035667A Lsi designing method and lsi designing device 审中-公开
标题翻译： LSI设计方法和LSI设计器件
公开(公告)号：JP2014035667A
公开(公告)日：2014-02-24
申请号：JP2012176874
申请日：2012-08-09
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： TERAYAMA TOSHIAKI , ISHIKAWA AYAYUKI
IPC分类号： G06F17/50 , H01L21/82 , H01L21/822 , H01L27/04
CPC分类号： G06F17/5072 , G06F17/5031 , G06F17/505 , G06F17/5068 , G06F17/5077 , G06F17/5081 , G06F2217/62
摘要： PROBLEM TO BE SOLVED: To optimize the number of steps of an upper clock tree without setting any restrictions on the arrangement of a lower clock tree when composing the upper out of H-trees and the lower out of CTS in an LSI designing method for designing a clock tree for supplying a clock signal to leaves from a clock supply point.SOLUTION: Leaves are divided into a plurality of groups and a lower local tree is formed. A clock supply target area including all the leaves of clock supply targets is equally divided. Having a clock supply point as an initial point, an upper clock tree using an H-tree is formed. For each area resulting from the division, a skew is estimated for supplying a clock signal to the initial point of a plurality of local trees, included in the area, from the terminal of the H-tree. Until the estimated skew satisfies a predetermined skew restriction, the clock supply target area is further equally divided into smaller areas to increase the number of the steps of the H-tree.
摘要翻译：要解决的问题：在LSI设计方法中，为了优化上层时钟树的步数，而不需要对构成H树上的较低时钟树的布置和CTS中较低的CTS的布置设置任何限制一个时钟树，用于提供从时钟供应点离开的时钟信号。解决方案：叶子被分成多个组，并且形成一个较低的局部树。包括时钟供应目标的所有叶片的时钟供应目标区域被均分。以时钟供应点作为初始点，形成使用H-tree的高时钟树。对于由分割产生的每个区域，估计从H树的终端向包括在该区域中的多个本地树的初始点提供时钟信号的偏差。在估计的偏移量达到预定的偏移限制之前，时钟供给目标区域被进一步等分成更小的区域以增加H树的步骤数量。

10. 发明专利

JP5326471B2 A method of designing a clock signal supply circuit, an information processing apparatus and program 有权
公开(公告)号：JP5326471B2
公开(公告)日：2013-10-30
申请号：JP2008254634
申请日：2008-09-30
申请人：富士通株式会社
发明人：達彦根岸
IPC分类号： G06F17/50 , G06F1/10 , G06F1/12 , H03K5/15 , H03K19/00
CPC分类号： G06F17/5031 , G06F2217/62
摘要： A clock signal providing circuit designing method for designing a clock signal providing circuit includes grouping circuit elements into a plurality of circuit groups each including a plurality of circuit elements, calculating an evaluation index value for each of the plurality of circuit groups and summing up calculated evaluation index values to obtain a first sum total, exchanging or moving provisionally at least one circuit element between the plurality of circuit groups, calculating an evaluation index value for each of the plurality of circuit groups and summing up calculated evaluation index values to obtain a second sum total, determining whether the second sum total decreases from the first sum total, fixing the circuit element provisionally exchanged or moved when the second sum total decreases from the first sum total and cancelling the circuit element provisionally exchanged or moved when the second sum total increases from the first sum total.

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