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1. 发明专利

JP2012173832A Layout method for semiconductor integrated circuit and program 有权
标题翻译：半导体集成电路和程序的布局方法
公开(公告)号：JP2012173832A
公开(公告)日：2012-09-10
申请号：JP2011032775
申请日：2011-02-18
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： SHUDO KENTA , SHIBATANI SATOSHI , ISHIKAWA AYAYUKI , SAITO TAKESHI , INOUE YOSHIO
IPC分类号： G06F17/50 , H01L21/82 , H01L21/822 , H01L27/04
CPC分类号： G06F17/5022 , G06F17/5068 , G06F2217/78 , G06F2217/84
摘要： PROBLEM TO BE SOLVED: To automatically create a power domain.SOLUTION: A computer performs: function simulation processing (9) for evaluating whether a designed circuit satisfies a specification; and cluster division processing (10) for obtaining a power domain by performing a cluster division for each logical block having activation timings within a predetermined range on the basis of the result of the function simulation processing. Thus, the power domain is obtained by the processing of the computer, thereby allowing a better optimization of a power domain than when it is obtained manually (by a manual operation of a designer).
摘要翻译：要解决的问题：自动创建电源域。解决方案：计算机执行：功能模拟处理（9），用于评估设计电路是否满足规范; 以及用于通过基于功能模拟处理的结果对具有在预定范围内的激活定时的每个逻辑块执行集群划分来获得功率域的集群分割处理（10）。因此，通过计算机的处理获得功率域，从而比手动获得（通过设计者的手动操作）更好地优化功率域。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2014035667A Lsi designing method and lsi designing device 审中-公开
标题翻译： LSI设计方法和LSI设计器件
公开(公告)号：JP2014035667A
公开(公告)日：2014-02-24
申请号：JP2012176874
申请日：2012-08-09
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： TERAYAMA TOSHIAKI , ISHIKAWA AYAYUKI
IPC分类号： G06F17/50 , H01L21/82 , H01L21/822 , H01L27/04
CPC分类号： G06F17/5072 , G06F17/5031 , G06F17/505 , G06F17/5068 , G06F17/5077 , G06F17/5081 , G06F2217/62
摘要： PROBLEM TO BE SOLVED: To optimize the number of steps of an upper clock tree without setting any restrictions on the arrangement of a lower clock tree when composing the upper out of H-trees and the lower out of CTS in an LSI designing method for designing a clock tree for supplying a clock signal to leaves from a clock supply point.SOLUTION: Leaves are divided into a plurality of groups and a lower local tree is formed. A clock supply target area including all the leaves of clock supply targets is equally divided. Having a clock supply point as an initial point, an upper clock tree using an H-tree is formed. For each area resulting from the division, a skew is estimated for supplying a clock signal to the initial point of a plurality of local trees, included in the area, from the terminal of the H-tree. Until the estimated skew satisfies a predetermined skew restriction, the clock supply target area is further equally divided into smaller areas to increase the number of the steps of the H-tree.
摘要翻译：要解决的问题：在LSI设计方法中，为了优化上层时钟树的步数，而不需要对构成H树上的较低时钟树的布置和CTS中较低的CTS的布置设置任何限制一个时钟树，用于提供从时钟供应点离开的时钟信号。解决方案：叶子被分成多个组，并且形成一个较低的局部树。包括时钟供应目标的所有叶片的时钟供应目标区域被均分。以时钟供应点作为初始点，形成使用H-tree的高时钟树。对于由分割产生的每个区域，估计从H树的终端向包括在该区域中的多个本地树的初始点提供时钟信号的偏差。在估计的偏移量达到预定的偏移限制之前，时钟供给目标区域被进一步等分成更小的区域以增加H树的步骤数量。

3. 发明专利

JP2013171503A Lsi design method 有权
标题翻译： LSI设计方法
公开(公告)号：JP2013171503A
公开(公告)日：2013-09-02
申请号：JP2012036097
申请日：2012-02-22
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： ISHIKAWA AYAYUKI , KOBAYAKAWA OSAMU
IPC分类号： G06F17/50 , H01L21/82
CPC分类号： G06F17/5045 , G06F17/5068 , G06F17/5077 , G06F2217/62 , G06F2217/78 , G06F2217/84 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： PROBLEM TO BE SOLVED: To reduce power consumption in a clock tree by more actively reducing a buffer on a clock tree as long as there exists a setup margin.SOLUTION: An object buffer as a deletion candidate is specified under the consideration of a branch in a clock tree, and the whole or a part of FF groups to be connected are defined as object FF and any FF other than the object FF is defined as non-object FF in a partial tree as a part of the clock tree extended from the branch under consideration. In this case, the object buffer as the deletion candidate and the object and non-object FF are specified so that any slack on a signal propagation path between the non-object FF can be prevented from fluctuating in principle even when the buffer is deleted. The buffer to be deleted is specified from among the object buffers and deleted within a range in which any setup violation does not occur on the signal propagation path with the non-object FF as a start point and the object FF as an end point and the signal propagation path of the inter-FF.
摘要翻译：要解决的问题：通过更有效地减少时钟树上的缓冲区来减少时钟树中的功耗，只要存在设置余量。解决方案：作为删除候选项的对象缓冲区是在分支的考虑下指定的时钟树，以及要连接的FF组的全部或一部分被定义为对象FF，并且除了对象FF之外的任何FF被定义为部分树中的非对象FF，作为从正在考虑中。在这种情况下，指定作为删除候选的对象缓冲器和对象和非对象FF，使得即使在缓冲器被删除的情况下，也可以防止在非对象FF之间的信号传播路径上的任何松弛原理波动。要删除的缓冲区是从对象缓冲区中指定的，并且在非对象FF作为起始点，以对象FF为终点的信号传播路径上不发生任何设置违规的范围内被删除，并且 FF间的信号传播路径。

4. 发明专利

JP2011209793A Method for design of semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件设计方法
公开(公告)号：JP2011209793A
公开(公告)日：2011-10-20
申请号：JP2010074219
申请日：2010-03-29
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： SHIBATANI SATOSHI , ISHIKAWA AYAYUKI , SHUDO KENTA
IPC分类号： G06F17/50 , H01L21/82
CPC分类号： G06F17/5072 , G06F17/5031 , G06F2217/84
摘要： PROBLEM TO BE SOLVED: To greatly reduce a layout change of cells after timing optimization to reduce a term taken for a layout design by estimating timing and an area after the timing optimization.SOLUTION: During initial layout processing using a net list 1, timing constraint 2, a floor plan 3, a layout library 4, and a timing library 5 or the like, a library for the timing/area estimation for estimating the timing and the area after the timing optimization is previously created, and it is estimated whether the timing constraint 2 can be satisfied. A cell present in a path hardly satisfying the timing constraint 2 is placed in proximity, and conversely, a cell easily satisfying the timing constraint 2 is placed at a distance. At this point, an area increase is also estimated, so that wiring congestion does not occur.
摘要翻译：要解决的问题：在定时优化之后大大减少单元的布局变化，通过估计定时和定时优化后的面积来减少布局设计所需的术语。解决方案：在使用网络列表1的初始布局处理期间，定时约束 2，平面图3，布局库4和定时库5等，预先创建用于估计定时和定时优化之后的区域的定时/区域估计的库，并且估计是否时间约束2可以满足。存在于几乎不满足定时约束2的路径中的单元被放置在接近的位置，相反地，容易满足定时约束2的单元被放置在一定距离处。此时，还估计面积增加，使得不发生布线拥塞。

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