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1. 发明专利

JP2005284893A Logic generation method of integrated circuit and logic generation program of integrated circuit 审中-公开
标题翻译：集成电路的逻辑生成方法和集成电路的逻辑生成程序
公开(公告)号：JP2005284893A
公开(公告)日：2005-10-13
申请号：JP2004100102
申请日：2004-03-30
申请人： Fujitsu Ltd , 富士通株式会社
发明人： IWAMOTO MASAMI , WATANABE GYOJI , KOMURA MAYUMI , SATO TETSUYA , SUZUKI NORIFUMI , NAKABAYASHI SEIJI
IPC分类号： G06F17/50 , H01L21/82
摘要： PROBLEM TO BE SOLVED: To shorten the logic design period of an integrated circuit by preventing connection mistakes of wiring and description mistakes when designing a logic. SOLUTION: In order to connect an IO cell to be connected to an external terminal, to a logic circuit, connection specifications of terminals of the IP cell and terminals of the logic circuit are inputted from the outside and circuit elements are automatically inserted between the IO cell and the logic circuit in accordance with the connection specifications. Then connection relations of elements constituting the integrated circuit are extracted to generate a netlist. Therefore, required circuit elements are surely inserted between the IO cell and the logic circuit in accordance with the connection specifications. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：设计逻辑时，通过防止接线错误和描述错误来缩短集成电路的逻辑设计周期。
解决方案：为了将要连接的外部端子的IO单元连接到逻辑电路，从外部输入IP单元的端子和逻辑电路的端子的连接规格，电路元件自动插入在IO单元和逻辑电路之间根据连接规格。然后，提取构成集成电路的元件的连接关系，生成网表。因此，根据连接规格，所需的电路元件可靠地插入在IO单元和逻辑电路之间。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2005141624A Verification apparatus, verification method, and program 有权
标题翻译：验证装置，验证方法和程序
公开(公告)号：JP2005141624A
公开(公告)日：2005-06-02
申请号：JP2003379532
申请日：2003-11-10
申请人： Fujitsu Ltd , 富士通株式会社
发明人： IWAMOTO MASAMI , OZAWA YUICHI
IPC分类号： G06F11/28 , G06F9/45 , G06F17/50
CPC分类号： G06F11/261 , G06F11/3696 , G06F17/5022
摘要： PROBLEM TO BE SOLVED: To efficiently conduct with good accuracy the verification of hardware and that of software in developing a system LSI.
SOLUTION: In verifying the hardware, an equivalent value verification section 13 compares a simulation result obtained from the logical simulator 11 of an HDL (Hardware Description Language) model 2 with an expected value generated by an expected value calculation model 12 for verification. In verifying the software, the expected value calculation model 12 is used through an interface section 15. A software debugger 14 verifies firmware 3. The expected value calculation model 12 is used as an expected value generation model in verifying the hardware, and used as the C model of the hardware in verifying the software. In this way, the expected value calculation model 12 is used for both of the hardware verification and the software verification. Thus, the verification is efficiently performed with good accuracy.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：在开发系统LSI时，以高精度高效地进行硬件和软件的验证。解决方案：在验证硬件时，等效值验证部分13将从HDL（硬件描述语言）模型2的逻辑模拟器11获得的仿真结果与期望值计算模型12产生的期望值进行比较，以进行验证。在验证软件时，期望值计算模型12通过接口部分15使用。软件调试器14验证固件3.期望值计算模型12用作验证硬件的预期值生成模型，并用作 C型硬件在验证软件时。以这种方式，期望值计算模型12用于硬件验证和软件验证两者。因此，能够高精度地进行验证。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2004086406A Operation verification method of processor and operation verification system of processor 审中-公开
公开(公告)号：JP2004086406A
公开(公告)日：2004-03-18
申请号：JP2002244639
申请日：2002-08-26
申请人： Fujitsu Ltd , 富士通株式会社
发明人： TANAKA HIROYUKI , IWAMOTO MASAMI , KOMURA MAYUMI , SUZUKI NORIFUMI , WATANABE GYOJI
IPC分类号： G06F17/50
摘要： PROBLEM TO BE SOLVED: To improve efficiency in verification of a processor by reducing time required for verification by comparison after the execution of a simulation.
SOLUTION: A software simulator and a hardware simulator which execute a test pattern are synchronously controlled and individually operated for every command a processor executes. Then, the results of the simulations are compared, and whether the descriptions of the software simulator and hardware simulator accord with each other is determined at least in one command unit. A location where an error occurs is quickly specified, since the quantity of the simulation result to be compared at a time decreases. Consequently, the verification by comparison after the execution of the simulation is efficiently executed, and a period of time required for the development of a processor can be reduced due to the efficient execution of the operation verification.
COPYRIGHT: (C)2004,JPO

4. 发明专利

JP2004030124A Development support cooperation device for semiconductor device and method for supporting development 有权
公开(公告)号：JP2004030124A
公开(公告)日：2004-01-29
申请号：JP2002184159
申请日：2002-06-25
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SATO TETSUYA , IWAMOTO MASAMI , ITO MASAYA , OZAWA YUICHI
IPC分类号： G06F17/50 , G06F11/22 , G06F11/26
CPC分类号： G06F11/261
摘要： PROBLEM TO BE SOLVED: To allow highly accurate debugging or operation confirmation. SOLUTION: The communication control means 123 of an emulator stub 120 obtains information on an event generated by a debugger stub 210 in accordance with an event generated in a debugger 210 and transmitted through a communication network 300. An emulator control means 121 analyzes the obtained information on event, controls an emulator 110 in accordance with the analyzed event, and executes emulation processing virtually reproducing the operation of a semiconductor device for the event based on information on hardware design. An event result generated in accordance with the pseudo-operation of the semiconductor device virtually reproduced by the emulator 110 is obtained. The event result is informed through the communication network 300 and the debugger stub 230 to the debugger 210 as necessary. COPYRIGHT: (C)2004,JPO

5. 发明专利

JP2005284426A Asynchronous circuit verification method and asynchronous circuit verification program 有权
标题翻译：异步电路验证方法和异步电路验证程序
公开(公告)号：JP2005284426A
公开(公告)日：2005-10-13
申请号：JP2004094030
申请日：2004-03-29
申请人： Fujitsu Ltd , 富士通株式会社
发明人： IKEDA NORIYUKI , IWAMOTO MASAMI , KIKUCHI HIROE , IKEUCHI KENTARO , TSURUTA YOICHI , SONODA JUNJI , WATANABE ATSUSHI
IPC分类号： G06F17/50 , G06F1/10
CPC分类号： G06F17/5059 , G06F17/5018 , G06F2217/62 , G06F2217/84 , G06F2217/86
摘要： PROBLEM TO BE SOLVED: To efficiently and accurately perform the operation verification of an asynchronous circuit. SOLUTION: An asynchronous list 12 is generated by extracting all asynchronous parts from an RTL1 by an asynchronous extraction program 11, and a control task inserting part 20 generates a control card 21 for controlling a clock/delay control part 40 and inserts a control task inserted into the RTL1. In a logic simulation stage by a simulator 33 for an RTL 31 into which the control task is inserted, the clock/delay control part 40 is linked with the simulator 33, and a modulation clock or a delay signal is inserted into the control task of the RTL 31. Thus, various delay states are prepared in the logic simulation stage of the RTL31 prior to logic synthesis, and to accurately and efficiently perform the operation verification of the asynchronous circuit. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：有效和准确地执行异步电路的操作验证。解决方案：通过由异步提取程序11从RTL1提取所有异步部分来产生异步列表12，并且控制任务插入部分20生成用于控制时钟/延迟控制部分40的控制卡21，并插入控制任务插入RTL1。在由控制任务插入的RTL 31的仿真器33的逻辑仿真阶段中，时钟/延迟控制部分40与仿真器33相连，调制时钟或延迟信号被插入到因此，在逻辑合成之前，在RTL31的逻辑仿真阶段中准备了各种延迟状态，并准确而有效地执行异步电路的操作验证。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2004029947A Clock generating device and audio data processor 有权
公开(公告)号：JP2004029947A
公开(公告)日：2004-01-29
申请号：JP2002181743
申请日：2002-06-21
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KATO AKIO , IWAMOTO MASAMI , ASAMI HIROKAZU , MIURA MASAHITO
IPC分类号： G06F1/04 , G06F1/06 , G06F1/12 , H03K5/00 , H03K5/135
CPC分类号： G06F1/06 , G06F1/12 , H03K5/135 , H03K2005/00247
摘要： PROBLEM TO BE SOLVED: To provide a clock generating device for generating a word clock following the change of a timing without inputting hardware reset or software reset from the outside. SOLUTION: This clock generating device is provided with a first clock generating circuit for outputting a clock by carrying out state transition synchronously with a master clock when a predetermined state is released in response to a timing signal supplied from the outside, a counter for counting the master clock when a reset state is released in response to the timing signal, and a reset circuit for resetting the counter when the count reaches a first predetermined value, and for setting the first clock generating circuit to a predetermined state. COPYRIGHT: (C)2004,JPO

7. 发明专利

JPH10207865A DIGITAL SIGNAL PROCESSING CIRCUIT 失效
公开(公告)号：JPH10207865A
公开(公告)日：1998-08-07
申请号：JP985497
申请日：1997-01-23
申请人： FUJITSU LTD
发明人： KONDO MASAYA , ASAMI HIROKAZU , IWAMOTO MASAMI , YOMO TAKASHI , KOBAYASHI MARI
IPC分类号： G06F7/38 , G06F17/10
摘要： PROBLEM TO BE SOLVED: To obtain a clip vale that application requires with a small process quality by performing product sum operation efficiently as to the digital signal processing circuit which can perform product-sum operation with a repeat instruction. SOLUTION: When the product-sum operation is carried out with the repeat instruction, the output of a product-sum arithmetic circuit 8 is transferred to an accumulator 13 through a selector 14 unless the output of the circuit 8 overflows, and if the output of the circuit 8 overflows halfway in the product- sum operation, a repeat instruction control circuit 11 ends the repeat instruction and also transfers a clip value store in a clip value storage register 12 to the accumulator 13 through the selector 14.

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