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1. 发明专利

JP2014038904A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2014038904A
公开(公告)日：2014-02-27
申请号：JP2012179379
申请日：2012-08-13
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： UCHIYAMA SHIRO
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/12 , H01L23/32 , H01L23/522 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L23/5384 , H01L21/486 , H01L21/76898 , H01L23/481 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2924/13091 , H01L2924/15311 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To suppress noise propagation between through electrodes in a semiconductor device having the through electrodes.SOLUTION: A substrate layer 116 has a plurality of through holes 122. Through electrodes 124 are formed in the through holes 122. A wring layer 118 is formed on the substrate layer 116. A plurality of wires are formed in the wiring layer 118, and some of the wires are connected to the through electrodes 124. Inner walls of the through holes 122 are covered with a metal film 128, and an oxide film 126 (insulating film) is formed on the metal film 128. A ground potential is supplied from a ground line 134 of the wiring layer 118 to the metal film 128.
摘要翻译：要解决的问题：抑制具有贯通电极的半导体器件中的通孔之间的噪声传播。解决方案：衬底层116具有多个通孔122.贯通电极124形成在通孔122中。绞合层118 形成在基板层116上。多根导线形成在布线层118中，并且一些导线与通孔124连接。通孔122的内壁被金属膜128覆盖，并且在金属膜128上形成氧化膜126（绝缘膜）。从布线层118的接地线134向金属膜128提供接地电位。

2. 发明专利

JP2014033056A Film formation method for polyimide film, manufacturing method for semiconductor device, and film formation device 审中-公开
标题翻译：聚酰亚胺薄膜的成膜方法，半导体器件的制造方法和薄膜形成装置
公开(公告)号：JP2014033056A
公开(公告)日：2014-02-20
申请号：JP2012172344
申请日：2012-08-02
申请人： Hiroshima Univ , 国立大学法人広島大学 , Elpida Memory Inc , エルピーダメモリ株式会社
发明人： HARUKI MASASHI , TAKITO SHIGEKI , KIHARA SHINICHI , HORIKAWA MITSUHIRO , OIDE HIROYUKI
IPC分类号： H01L21/312 , C08G73/10 , H01L21/31
CPC分类号： H01L21/02118 , H01L21/02282 , H01L23/3171 , H01L25/50 , H01L2924/0002 , Y10T428/31721 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To efficiently form a polyimide film in conformity with a surface having a complicated shape.SOLUTION: A film formation method for a polyimide film is designed to form a polyimide film on a surface of a substrate arranged in a high-pressure polymerization cell. The film formation method for the polyimide film includes: supplying a diamine monomer dissolved in carbon dioxide in a supercritical state and tetracarboxylic dianhydride monomer dissolved in carbon dioxide in a supercritical state through independent supply paths respectively; and subjecting the diamine monomer and tetracarboxylic dianhydride monomer mixed nearby the substrate and reaching the surface of the substrate while dissolved in the carbon dioxide in the supercritical state, and a polyamide acid in which the diamine monomer and tetracarboxylic dianhydride monomer react, to reaction on the surface of the substrate.
摘要翻译：要解决的问题：有效地形成与具有复杂形状的表面一致的聚酰亚胺膜。解决方案：设计用于聚酰亚胺膜的成膜方法，以在高压下布置的基板的表面上形成聚酰亚胺膜聚合电池。聚酰亚胺膜的成膜方法包括：分别以超临界状态提供溶解在超临界状态的二氧化碳中的二胺单体和分别以超临界状态溶解在二氧化碳中的四羧酸二酐单体; 并且将二胺单体和四羧酸二酐单体混合在基体附近并溶解在超临界状态的二氧化碳中并到达基板的表面，以及其中二胺单体和四羧酸二酐单体反应的聚酰胺酸，基板的表面。

3. 发明专利

JP2014032724A Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：JP2014032724A
公开(公告)日：2014-02-20
申请号：JP2012173091
申请日：2012-08-03
申请人： Sharp Corp , シャープ株式会社 , Elpida Memory Inc , エルピーダメモリ株式会社
发明人： ISHIHARA KAZUYA , TAMAI YUKIO , NAKANO TAKASHI , SEKO AKIYOSHI
IPC分类号： G11C13/00
CPC分类号： G11C13/0021 , G11C13/0007 , G11C13/0069 , G11C2213/79
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of performing efficient rewriting with low voltage and low current operation by including a variable resistive element.SOLUTION: The semiconductor storage device has a memory cell array configured by arranging a plurality of memory cells obtained by connecting variable resistive element and a selection transistor in series in the shape of a matrix. A set operation (low resistance operation of variable resistive element) of a memory cell is performed by applying a set voltage pulse, taking a time longer than in a reset operation (high resistance operation of variable resistive element) while the selection transistor limits current flowing during the set operation to predetermined low current, and is performed by simultaneously applying the set voltage pulse to the plurality of memory cells.
摘要翻译：要解决的问题：提供一种能够通过包括可变电阻元件来进行低电压和低电流操作的高效重写的半导体存储装置。解决方案：半导体存储装置具有存储单元阵列，该存储单元阵列通过布置获得的多个存储单元通过将可变电阻元件和选择晶体管串联连接成矩阵形状。存储单元的设定操作（可变电阻元件的低电阻操作）通过施加设定电压脉冲来执行，该设定电压脉冲比复位操作时间长（可变电阻元件的高电阻操作），而选择晶体管限制电流流动在设定操作期间到预定的低电流，并且通过同时向多个存储单元施加设定电压脉冲来执行。

4. 发明专利

JP2014022652A Semiconductor device and test equipment therefor, and semiconductor device test method 审中-公开
标题翻译：半导体器件及其测试设备及半导体器件测试方法
公开(公告)号：JP2014022652A
公开(公告)日：2014-02-03
申请号：JP2012161806
申请日：2012-07-20
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： IKEDA HIROAKI
IPC分类号： H01L25/18 , H01L21/60 , H01L25/065 , H01L25/07
CPC分类号： G01R31/2601 , G01R31/2884 , G01R31/2889 , G11C29/025 , G11C2029/5006 , H01L2224/16145 , H01L2224/16225 , H01L2924/15311
摘要： PROBLEM TO BE SOLVED: To detect loose contact between bump electrodes in a layered semiconductor device by a simple method.SOLUTION: A semiconductor device comprises a semiconductor chip MC0 having a Driver circuit MD0 for driving a bump electrode FB0 and a semiconductor chip CC having a driver circuit CD for driving a bump electrode BBC. The semiconductor chips MC0, CC are layered one on the other in such a way as to make the bump electrodes FB0, BBC be electrically connected thereby to form a current path including the bump electrodes FB0, BBC. In a test mode, when the driver circuit CD drives the current path to second potential during the driver circuit MD0 drives the current path to first potential, bus fight occurs. By purposely increasing current consumption by the bus fight, a connection state of the bump electrodes can be evaluated only by monitoring a change in the current consumption.
摘要翻译：要解决的问题：通过简单的方法检测分层半导体器件中的凸起电极之间的松动接触。解决方案：半导体器件包括半导体芯片MC0，其具有用于驱动凸块电极FB0的驱动电路MD0和具有用于驱动凸起电极FB0的半导体芯片CC 用于驱动凸块电极BBC的驱动电路CD。半导体芯片MC0，CC以这样的方式层叠，以使凸块电极FB0，BBC电连接，从而形成包括凸起电极FB0，BBC的电流路径。在测试模式中，当驱动电路CD驱动当前路径到第二电位时，在驱动电路MD0将当前路径驱动到第一电位时，发生总线故障。通过有意地增加总线的电力消耗，可以仅通过监视电流消耗的变化来评估凸块电极的连接状态。

5. 发明专利

JP5355988B2 Thermal stress analysis method of electronic parts, resin flow analysis method and thermal stress analysis equipment 有权
公开(公告)号：JP5355988B2
公开(公告)日：2013-11-27
申请号：JP2008278269
申请日：2008-10-29
申请人：株式会社日立製作所 , エルピーダメモリ株式会社
发明人：務河野 , 眞行美野 , 英宏竹嶋 , 洋行伊藤 , 智子五井
IPC分类号： G06F17/50 , B29C45/76
CPC分类号： G01N3/00 , G01N2203/0214
摘要： A method of analyzing thermal stress includes calculating a distribution of the number of fillers in a composite integrally molded product by using physical property values of resin material containing fillers, and determining a coefficient of linear expansion of the resin material in the composite integrally molded product, that is used as an input condition of a thermal stress analysis, based on the distribution of the number of the fillers.

6. 发明专利

JP2013222901A Semiconductor device manufacturing method 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：JP2013222901A
公开(公告)日：2013-10-28
申请号：JP2012095041
申请日：2012-04-18
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： HASEGAWA SHIGERU
IPC分类号： H01L21/60 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/16145 , H01L2224/16225
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can inhibit occurrence of a short circuit between bump electrodes and form a solder layer having a sufficient thickness on a solder transfer surface of the bump electrode.SOLUTION: A semiconductor device manufacturing method comprises: heating a solder transferring jig 84 in which projections 85 having a second solder transfer surface 85a opposite to a first solder transfer surface of a semiconductor chip 11 are arranged on one surface 84a; subsequently sandwiching a solder transferring member with the projections 85 and a stage 55 to primarily transfer melted solder powder 77 on the second solder transfer surface 85a of the projections 85; subsequently heating the first semiconductor chip 11 and contacting the first solder transfer surface with the melted solder power which is primarily transferred to the second solder transfer surface 85a so as to secondary transfer the melted solder powder 77 to the first solder transfer surface; and subsequently, performing a reflow treatment to form a solder layer composed of the solder powder on the first solder transfer surface.
摘要翻译：要解决的问题：提供一种半导体器件制造方法，其可以抑制突起电极之间的短路发生，并在凸块电极的焊料转移面上形成具有足够厚度的焊料层。解决方案：半导体器件制造方法包括：加热焊料转移夹具84，其中具有与半导体芯片11的第一焊料转移表面相对的第二焊料转移表面85a的突起85布置在一个表面84a上; 随后将具有突起85和台55的焊料转移构件夹在一起，以将熔融的焊料粉末77主要转移到突起85的第二焊料转移表面85a上; 随后加热第一半导体芯片11并使第一焊料转移表面与主要转移到第二焊料转移表面85a的熔融焊料功率接触，以将熔融的焊料粉末二次二次转移到第一焊料转移表面; 并且随后进行回流处理以在第一焊料转移表面上形成由焊料粉末组成的焊料层。

7. 发明专利

JP2013219231A Semiconductor device manufacturing method 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：JP2013219231A
公开(公告)日：2013-10-24
申请号：JP2012089292
申请日：2012-04-10
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： KASHIWATANI EMI , ITO HIROYUKI , HATAKEYAMA KOICHI
IPC分类号： H01L21/60 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/16145 , H01L2224/32145 , H01L2224/73204 , H01L2924/15311 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor manufacturing method which can inhibit occurrence of a short circuit between bump electrodes and for a solder layer of a sufficient thickness on solder transfer surfaces of the bump electrodes.SOLUTION: A semiconductor device manufacturing method comprises: sucking another surface 62b of a chip laminate 62 by a bonding tool 58 and heating the chip laminate 62 and arranging a solder transfer surface 27a of a first surface bump electrode 21 and solder powder opposite to each other; subsequently transferring the bonding tool 58 downward and stopping transfer of the bonding tool 58 at a position where the solder transfer surface 27a touches the solder powder 77; subsequently melting the solder powder 77 by the heated first surface bump electrode 21 and transferring molten solder powder on the solder transfer surface 27a; and performing a reflow treatment on the molten solder powder 77 to form a solder layer composed of the solder powder 77 on the transfer surface 27a.
摘要翻译：要解决的问题：提供一种半导体制造方法，其可以抑制突起电极之间的短路发生，以及对于凸块电极的焊料转移面上的足够厚度的焊料层。解决方案：一种半导体器件制造方法，包括：通过接合工具58将芯片层压体62的另一个表面62b加热并加热芯片层压体62并且布置第一表面凸块电极21的焊料转移表面27a和彼此相对的焊料粉末; 随后向下转移接合工具58并阻止接合工具58在焊料转移表面27a接触焊料粉末77的位置处的转移; 随后通过加热的第一表面凸块电极21熔化焊料粉末77并将熔融焊料粉末转移到焊料转移表面27a上; 对熔融焊料粉末77进行回流处理，在转印面27a上形成由焊料粉末77构成的焊料层。

8. 发明专利

JP2013218767A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2013218767A
公开(公告)日：2013-10-24
申请号：JP2012089857
申请日：2012-04-11
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： ISHII TOSHINAO , NAGAMINE HISASHI
IPC分类号： G11C11/401 , G11C11/4096
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device including a data bus structure capable of transferring data in parallel and at a high speed by reducing a difference between far and close ends of a data bus connecting a data input/output section to a memory cell array and the like.SOLUTION: A semiconductor device comprises: a data bus; a data input-output section that is connected to the data bus, and inputs and outputs data transmitted through the data bus; and a plurality of bus interface sections each of which is connected to the data bus, and inputs and outputs data for the data input-output section through the data bus. The data bus is arranged and wired so that a wiring length of the data bus from each of the plurality of bus interface sections to the data input-output section becomes equal to each other.
摘要翻译：要解决的问题：提供一种包括数据总线结构的半导体器件，该数据总线结构能够通过将数据输入/输出部分连接到存储器单元的数据总线的远端和近端之间的差异并行传输和高速传输阵列等。解决方案：半导体器件包括：数据总线; 数据输入输出部分，连接到数据总线，并输入和输出通过数据总线发送的数据; 以及多个总线接口部分，每个总线接口部分连接到数据总线，并通过数据总线输入和输出数据输入 - 输出部分的数据。数据总线被布置和布线，使得从多个总线接口部分中的每一个到数据输入 - 输出部分的数据总线的布线长度变得彼此相等。

9. 发明专利

JP2013214611A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2013214611A
公开(公告)日：2013-10-17
申请号：JP2012083953
申请日：2012-04-02
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： TOMOHIRO TAKASHI
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L25/00 , H01L21/561 , H01L23/3128 , H01L24/97 , H01L25/0657 , H01L2224/05554 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/49175 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/92247 , H01L2224/97 , H01L2225/0651 , H01L2225/06517 , H01L2225/06558 , H01L2225/06562 , H01L2225/06568 , H01L2225/06575 , H01L2924/15183 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2224/85 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of achieving both cost reduction and stable assemblability.SOLUTION: The semiconductor device includes a wiring board, a first semiconductor chip mounted on the wiring board via a first adhesive member, and a second semiconductor chip laminated on the first semiconductor chip via a second adhesive member. The first adhesive member is a die attach film in which adhesive layers are provided on both surfaces of an insulating base material, and the second adhesive member is an adhesive paste.
摘要翻译：要解决的问题：提供能够实现成本降低和稳定组装的半导体器件。解决方案：半导体器件包括布线板，经由第一粘合部件安装在布线板上的第一半导体芯片和第二半导体芯片通过第二粘合构件层压在第一半导体芯片上。第一粘合部件是在绝缘基材的两面上设置有粘合剂层的管芯附着膜，第二粘合部件是粘合剂糊剂。

10. 发明专利

JP2013201526A Semiconductor device and input signal receiving circuit 审中-公开
标题翻译：半导体器件和输入信号接收电路
公开(公告)号：JP2013201526A
公开(公告)日：2013-10-03
申请号：JP2012067568
申请日：2012-03-23
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： KITAGAWA KATSUHIRO , KOBAYASHI KATSUTARO
IPC分类号： H03K19/0175
CPC分类号： H03K19/003 , H03K19/018521
摘要： PROBLEM TO BE SOLVED: To reduce power consumption of an input circuit.SOLUTION: A semiconductor device of a present embodiment comprises an input circuit which is connected between an input node and an output node for changing a level of the output node depending on a signal supplied to the input node. When a control signal indicates a first mode, the input circuit causes a transition speed of a level of the output node from a first level to a second level to be higher than a transition speed of the level from the second level to the first level, and when the control signal indicates a second mode different from the first mode, the input circuit causes a transition speed of the level of the output node from the second level to the first level to be higher than a transition speed of the level from the first level to the second level.
摘要翻译：要解决的问题：降低输入电路的功耗。本实施例的半导体器件包括输入电路，其连接在输入节点和输出节点之间，用于根据信号改变输出节点的电平提供给输入节点。当控制信号指示第一模式时，输入电路使得输出节点的电平从第一电平到第二电平的转换速度高于从第二电平到第一电平的电平的转换速度，并且当所述控制信号指示与所述第一模式不同的第二模式时，所述输入电路使得所述输出节点的电平从所述第二电平到所述第一电平的转变速度高于从所述第一电平的电平的转变速度级到第二级。

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