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    • 5. 发明专利
    • AFC DEVICE FOR PSK RECEIVER
    • JPH07115448A
    • 1995-05-02
    • JP26216293
    • 1993-10-20
    • UCHU TSUSHIN KISO GIJUTSU KENK
    • YAMAMOTO TETSUO
    • H04L27/227
    • PURPOSE:To follow fast frequency fluctuation and to converge a phase error at high speed. CONSTITUTION:A 4-phase PSK modulation signal is orthogonally detected by an orthogonal detector 12, and it is passed through a root cosine filter 17, and is sampled with a symbol period at a sampling circuit 18, and the phase error is detected by a phase error detecting part 19. When the absolute value of difference between the phase error and the one last time exceeds pi/4, a correction part 21 adds or subtracts pi/2 so as to set the absolute value of the difference at a value less than pi/4, and supplies it to a low-pass filter 22, and controls a local oscillator 13 by the output of the filter. When the phase of the output of the filter 22 exceeds pi/2, a correction reset part 31 detects the fact, and clears the internal state of the filter 22, and also, interrupts correction control for the local oscillator 13, and interrupts correction by a correction part 21.
    • 8. 发明专利
    • GROUP DEMODULATOR FOR PHASE MODULATION SIGNAL
    • JPH07177189A
    • 1995-07-14
    • JP31846593
    • 1993-12-17
    • UCHU TSUSHIN KISO GIJUTSU KENK
    • YAMAMOTO TETSUOMARUYAMA HIDEYUKIOTSUTSU YUUICHIOKAMOTO TERUYOSHIISHIKAWA MAMORU
    • H04L27/22H04B7/185H04J1/00
    • PURPOSE:To provide a group demodulator provided to a satellite equipment with a small size, light weight and low power consumption. CONSTITUTION:An input FDM signal is converted and separated into a base band digital signal for each channel and fed to a deviation detection means 31 and a multiplex circuit 45. The signal is inserted into each channel, its instantaneous power is detected and a minimum variance based on each reference clock is detected by a detection means 36 as a clock timing ts of a symbol in the deviation detection means 31. An output of an insertion filter 34 is sampled in the timing and a phase angle theta as to data is detected from the sample value and an error frequency and phase are detected. A cosine and a sine signal of the error frequency and phase are subjected to complex multiplication to a phase modulation signal corresponding to each channel by a correction means 46, the carrier is corrected and the corrected signal is separately stored in start-stop memories 491-49m, and a delay corresponding to the ts of each channel is given to the start-stop memories 491-49m and an output of each start-stop memory is stored in buffer circuits 511-51m and inputted to a filter for each channel at a multiplex circuit and an impulse response is interpolated and the resulting signal is regenerated.
    • 10. 发明专利
    • QPSK PREAMBLE SIGNAL GENERATOR
    • JPH07183926A
    • 1995-07-21
    • JP32740793
    • 1993-12-24
    • UCHU TSUSHIN KISO GIJUTSU KENK
    • YAMAMOTO TETSUOMARUYAMA HIDEYUKI
    • H04L27/22
    • PURPOSE:To enable clock extraction even when a frequency error is 9 large by repeatedly generating a signal obtained by inverting both an in-phase signal of symbol values of QPSK and an orthogonal signal, and a signal obtained by inverting one of them, each a specific number of times. CONSTITUTION:Pattern generating means 11 and 12 input the in-phase signal I and orthogonal signal Q outputted from a register 13, and the means 11 inverts the signs of both the signals I and Q and outputs them. The means 12, on the other hand, generates the signal, obtained by inverting the signal I while the signal Q is not inverted, and the signal obtained by inverting the signal Q while the signal I is not inverted, alternately at intervals of (r) times. One of the signals I and Q generated by the means 11 and 12 respectively is selected by a selector 14 and the signals I or Q is outputted through the output register 13. This constitution provides variation passing through an origin on an IQ plane and facilitates the extraction of a clock.