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1. 发明专利

JPH06252652A VOLTAGE CONTROLLED FREQUENCY SYNCHRONIZATION OSCILLATOR 失效
公开(公告)号：JPH06252652A
公开(公告)日：1994-09-09
申请号：JP3388893
申请日：1993-02-24
申请人： FUJITSU LTD , UCHU TSUSHIN KISO GIJUTSU KENK
发明人： SHIGAKI MASAFUMI , YAMAMOTO TETSUO , HONGO HIRONOBU , ADACHI AKIFUMI , IWATSUKI MASANORI
IPC分类号： H03D13/00
摘要： PURPOSE:To obtain a low noise signal at a more stable frequency by connecting a phase shifter whose phase shift is changed with a control voltage to any position among for positions at each of pre-stage and post-stage of reference and comparison lines so as to obtain an optional frequency signal. CONSTITUTION:A signal via a reference line 3 and a phase shifter 5 and a signal via a comparison line 4 are inputted to a mixer circuit 7, in which the phases of the signals are compared. The result of comparison as an error signal is inputted to a voltage controlled oscillator 1 via a loop filter circuit 8. That is, the oscillating frequency of the oscillator 1 is controlled in response to the error signal received via the circuit 8 and the oscillator 1 outputs a signal 2. Since a phase shift of the phase shifter 5 varies with a control voltage 6, a desired frequency signal 2 is obtained by setting the control voltage optionally. As a result, an event of obtaining only a single frequency signal 2 is avoided and the desired frequency signal is obtained even when the phase shifter 5 is connected to any of pre-stages and post-stages of the reference line and the comparison line 4.

2. 发明专利

JPH06152243A EXTRA-HIGH FREQUENCY OSCILLATOR 失效
公开(公告)号：JPH06152243A
公开(公告)日：1994-05-31
申请号：JP29970092
申请日：1992-11-10
申请人： FUJITSU LTD , UCHU TSUSHIN KISO GIJUTSU KENK
发明人： SHIGAKI MASAFUMI , YAMAMOTO TETSUO , IWATSUKI MASANORI , HONGO HIRONOBU , ADACHI AKIFUMI
IPC分类号： H03B5/18
摘要： PURPOSE:To reduce the number of constituting parts with respect to the ultra- high frequency oscillator used in a microwave and millimeter wave communication equipment. CONSTITUTION:An oscillating means which has an oscillating element and a resonator having a frequency (f) and is oscillated with the frequency (f) and an amplifying means 3 which is operated with a frequency f/2 are provided, and such loop is formed that the output of the oscillating means is applied to the input side of the amplifying means and the output of the amplifying means is applied to the input side of the oscillating means, and the signal component having the frequency f/2 is taken out from the output of the oscillating means and is applied to the oscillating means through the amplifying means.

3. 发明专利

JPH06152400A PHASE SYNCHRONIZING OSCILLATION CIRCUIT 失效
公开(公告)号：JPH06152400A
公开(公告)日：1994-05-31
申请号：JP29969992
申请日：1992-11-10
申请人： FUJITSU LTD , UCHU TSUSHIN KISO GIJUTSU KENK
发明人： SHIGAKI MASAFUMI , YAMAMOTO TETSUO , IWATSUKI MASANORI , HONGO HIRONOBU , ADACHI AKIFUMI
IPC分类号： H03B5/12 , H03L7/099
摘要： PURPOSE:To simplify the circuit constitution of a phase synchronizing oscillator to be used in a local oscillator in a communication equipment for a microwave band and a milliwave band. CONSTITUTION:In the phase synchronizing oscillation circuit having an oscillator 4 connecting an input side line connected with a dielectric resonator having resonance frequency f0 to the gate of an FET to impress bias voltage, connecting an output side line to the drain to impress drain voltage and allowed to extract an oscillation signal with the resonance frequency f0 from an output line and a phase comparing part 3 for comparing the phase of an impressed reference signal with that of an oscillation signal, obtaining a phase difference signal corresponding to the phase difference, removing an unnecessary component in the phase difference signal, and outputting the processed signal as frequency controlling voltage and constituted so as to output an oscillation signal synchronized with the reference signal, superposed voltage obtained by superposing the frequency controlling voltage to impressed prescribed DC voltage is impressed to the gate as bias voltage to control the oscillation frequency of the FET.

4. 发明专利

JPH07123064A GROUPING DEMODULATOR FOR PHASE MODULATION SIGNAL 失效
公开(公告)号：JPH07123064A
公开(公告)日：1995-05-12
申请号：JP26380893
申请日：1993-10-21
申请人： UCHU TSUSHIN KISO GIJUTSU KENK
发明人： YAMAMOTO TETSUO
IPC分类号： H04L27/22 , H04J1/00
摘要： PURPOSE:To attain small size, light weight, low cost and to reduce power consumption. CONSTITUTION:An input signal is converted into a base band signal for each channel at a separation conversion part 19, sampled at carrier correction circuits 221-22m in a clock timing to correct a deviation of a carrier with respect to a reference signal. Each base band signal is received by a common arithmetic section 31 for an input initial state and the part 31 detects instantaneous power of each channel and a sampling point minimizing a variance of each sample point of the instantaneous power is used for a clock timing. Then the channel is sampled in the clock timing to detect a phase error and a frequency and phase deviation with respect to a reference frequency and phase, the clock timing is set to a clock recovery circuit in a carrier correction circuit of a corresponding channel and a frequency deviation and a phase deviation are set to a local oscillator respectively.

5. 发明专利

JPH07115448A AFC DEVICE FOR PSK RECEIVER 失效
公开(公告)号：JPH07115448A
公开(公告)日：1995-05-02
申请号：JP26216293
申请日：1993-10-20
申请人： UCHU TSUSHIN KISO GIJUTSU KENK
发明人： YAMAMOTO TETSUO
IPC分类号： H04L27/227
摘要： PURPOSE:To follow fast frequency fluctuation and to converge a phase error at high speed. CONSTITUTION:A 4-phase PSK modulation signal is orthogonally detected by an orthogonal detector 12, and it is passed through a root cosine filter 17, and is sampled with a symbol period at a sampling circuit 18, and the phase error is detected by a phase error detecting part 19. When the absolute value of difference between the phase error and the one last time exceeds pi/4, a correction part 21 adds or subtracts pi/2 so as to set the absolute value of the difference at a value less than pi/4, and supplies it to a low-pass filter 22, and controls a local oscillator 13 by the output of the filter. When the phase of the output of the filter 22 exceeds pi/2, a correction reset part 31 detects the fact, and clears the internal state of the filter 22, and also, interrupts correction control for the local oscillator 13, and interrupts correction by a correction part 21.

6. 发明专利

JPH07115446A CLOCK REGENERATOR FOR DIGITAL PHASE MODULATION 失效
公开(公告)号：JPH07115446A
公开(公告)日：1995-05-02
申请号：JP26216093
申请日：1993-10-20
申请人： UCHU TSUSHIN KISO GIJUTSU KENK
发明人： MARUYAMA HIDEYUKI , YAMAMOTO TETSUO
IPC分类号： H04L27/22 , H04L7/033
摘要： PURPOSE:To find a clock decision point correctly and with small computing quantity even when carrier frequency difference exists between an input signal and a local signal. CONSTITUTION:The input signal is orthogonally detected by an orthogonal detector 17, and each detected output is supplied to square devices 23, 24 via poliphase filters 21, 22, and the output of them are squared, respectively, and they are added by an adder 25, then, a momentary power is detected. The momentary power delayed by a one symbol delay device 27 is subtracted by a subtractor 26. The power is sampled at 1/2 symbol period, and the lead/lag of a clock is discriminated from the codes of three sampling values by a discrimination part 29 so that the center sampling value of continuous three points can be set at zero and the codes of the sampling values before and behind can be set reversely, and either one of poliphase filters 21, 22 is selected sequentially corresponding to the discriminated result.

7. 发明专利

JPH05128974A RADIATION COOLING TYPE COLLECTOR BODY STRUCTURE FOR MICROWAVE TUBE 失效
公开(公告)号：JPH05128974A
公开(公告)日：1993-05-25
申请号：JP6012391
申请日：1991-03-25
申请人： UCHU TSUSHIN KISO GIJUTSU KENK
发明人： ATSUKAWA SUSUMU , AOKI YASUHIRO , YAMAMOTO TETSUO
IPC分类号： H01J23/033
摘要： PURPOSE:To cool a collector electrode efficiently. CONSTITUTION:In one end of a stainless cylindrical envelope 41, an end plate 42 of beryllia is welded to block the end, a cylindrical electrode periphery holder 43 is projected and formed integrally on the inner surface of the end plate 42, a collector electrode 15 is welded opposing to the inner circumferential surface of the electrode periphery holder 43, and the peripheries of electrodes 14, 13, 12, and 11 which have electron beam passing holes are superposed in order and welded to the projecting end face of the electrode periphery holder 43 through beryllia ring-form spacers 44, 45, and 46. The heat of the electrodes 11 to 15 is transmitted to the end plate 42 and the envelope 41 by the conduction through the spacers 44 to 46.

8. 发明专利

JPH07177189A GROUP DEMODULATOR FOR PHASE MODULATION SIGNAL 失效
公开(公告)号：JPH07177189A
公开(公告)日：1995-07-14
申请号：JP31846593
申请日：1993-12-17
申请人： UCHU TSUSHIN KISO GIJUTSU KENK
发明人： YAMAMOTO TETSUO , MARUYAMA HIDEYUKI , OTSUTSU YUUICHI , OKAMOTO TERUYOSHI , ISHIKAWA MAMORU
IPC分类号： H04L27/22 , H04B7/185 , H04J1/00
摘要： PURPOSE:To provide a group demodulator provided to a satellite equipment with a small size, light weight and low power consumption. CONSTITUTION:An input FDM signal is converted and separated into a base band digital signal for each channel and fed to a deviation detection means 31 and a multiplex circuit 45. The signal is inserted into each channel, its instantaneous power is detected and a minimum variance based on each reference clock is detected by a detection means 36 as a clock timing ts of a symbol in the deviation detection means 31. An output of an insertion filter 34 is sampled in the timing and a phase angle theta as to data is detected from the sample value and an error frequency and phase are detected. A cosine and a sine signal of the error frequency and phase are subjected to complex multiplication to a phase modulation signal corresponding to each channel by a correction means 46, the carrier is corrected and the corrected signal is separately stored in start-stop memories 491-49m, and a delay corresponding to the ts of each channel is given to the start-stop memories 491-49m and an output of each start-stop memory is stored in buffer circuits 511-51m and inputted to a filter for each channel at a multiplex circuit and an impulse response is interpolated and the resulting signal is regenerated.

9. 发明专利

JPH07183926A QPSK PREAMBLE SIGNAL GENERATOR 失效
公开(公告)号：JPH07183926A
公开(公告)日：1995-07-21
申请号：JP32740793
申请日：1993-12-24
申请人： UCHU TSUSHIN KISO GIJUTSU KENK
发明人： YAMAMOTO TETSUO , MARUYAMA HIDEYUKI
IPC分类号： H04L27/22
摘要： PURPOSE:To enable clock extraction even when a frequency error is 9 large by repeatedly generating a signal obtained by inverting both an in-phase signal of symbol values of QPSK and an orthogonal signal, and a signal obtained by inverting one of them, each a specific number of times. CONSTITUTION:Pattern generating means 11 and 12 input the in-phase signal I and orthogonal signal Q outputted from a register 13, and the means 11 inverts the signs of both the signals I and Q and outputs them. The means 12, on the other hand, generates the signal, obtained by inverting the signal I while the signal Q is not inverted, and the signal obtained by inverting the signal Q while the signal I is not inverted, alternately at intervals of (r) times. One of the signals I and Q generated by the means 11 and 12 respectively is selected by a selector 14 and the signals I or Q is outputted through the output register 13. This constitution provides variation passing through an origin on an IQ plane and facilitates the extraction of a clock.

10. 发明专利

JPH07162467A CLOCK EXTRACTOR 失效
公开(公告)号：JPH07162467A
公开(公告)日：1995-06-23
申请号：JP33807193
申请日：1993-12-28
申请人： UCHU TSUSHIN KISO GIJUTSU KENK
发明人： YAMAMOTO TETSUO , MARUYAMA HIDEYUKI
IPC分类号： H04L27/22
摘要： PURPOSE:To correctly extract clock timing even if there is a frequency offset between an input signal carrier and a local signal. CONSTITUTION:Quadrature detection is performed for the input signal, the I signal and Q signal of the detection output are squared respectively and summed together, and an extractor 24 calculates the square root. Variance values at respective sample points in one symbol period of the output of the extractor 24 are calculated by a computing element 25. A decision means 27 decides the minimum value among the variance values and outputs the sampling point corresponding to the minimum value as clock timing. The variation state of the variance values becomes a curve 28 and the eye pattern of momentary electric power has an envelope maximum value 38 and a minimum value 35.

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