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1. 发明专利

JP2010278259A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010278259A
公开(公告)日：2010-12-09
申请号：JP2009129553
申请日：2009-05-28
申请人： Toyota Motor Corp , トヨタ自動車株式会社
发明人： HISANAGA YUKIHIRO , KANEHARA HIROMICHI
IPC分类号： H01L29/78 , H01L21/336 , H01L27/04 , H01L29/12 , H01L29/739
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device equipped with an IGBT and a diode where a reverse current is not generated easily during a recovery operation of the diode, and an on-voltage of the IGBT is low.
SOLUTION: In the semiconductor device equipped with the IGBT and a diode, the n-type emitter region 22 of the IGBT, the p-type body region 24 of the IGBT, and the p-type anode region 24 of the diode are formed to face the upper surface 12a of a semiconductor substrate 12, the p-type collector region 28 of the IGBT, and the n-type cathode region 30 of the diode are formed to face the lower surface 12b of the semiconductor substrate 12, and the n-type drift region 26 having an n-type impurity concentration lower than that of the n-type cathode region 30 is formed on the semiconductor substrate 12 to separate the region at the upper surface side and the region at the lower surface side where a part of the n-type drift region 26 is formed of an SiGe semiconductor 29.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了提供配备有IGBT和二极管的半导体器件，其中在二极管的恢复操作期间不容易产生反向电流，并且IGBT的导通电压低。解决方案：在装备有IGBT和二极管的半导体器件中，IGBT的n型发射极区域22，IGBT的p型体区域24和二极管的p型阳极区域24 形成为面对半导体基板12的上表面12a，IGBT的p型集电极区域28和二极管的n型阴极区域30形成为面对半导体基板12的下表面12b，并且在半导体基板12上形成具有比n型阴极区30低的n型杂质浓度的n型漂移区26，以分离上表面侧的区域和下表面侧的区域其中n型漂移区26的一部分由SiGe半导体29形成。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2008186839A Method of manufacturing semiconductor substrate 有权
标题翻译：制造半导体基板的方法
公开(公告)号：JP2008186839A
公开(公告)日：2008-08-14
申请号：JP2007016538
申请日：2007-01-26
申请人： Toyota Motor Corp , トヨタ自動車株式会社
发明人： HISANAGA YUKIHIRO , OKUMURA KATSUYA
IPC分类号： H01L21/316 , H01L21/336 , H01L29/739 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor substrate in which an SiO
2 film, having a uniform thickness and high insulation, is formed on its surface.
SOLUTION: The method of manufacturing a semiconductor substrate, in which an SiO
2 film is formed on the surface of a silicon substrate 40, has an SiO
2 film forming step S4 for forming an SiO
2 film 44 on the surface of the silicon substrate 40 by a chemical vapor phase growing method that uses organic gas; a decarbonizing preliminary step S6 for decreasing the carbon density in the SiO
2 film 44, by applying heat treatment to the silicon substrate 40 subjected to the SiO
2 film forming step in an inert gas atmosphere; and an additional decarbonizing step S8 for further decreasing the carbon density in the SiO
2 film 44, by applying heat treatment to the silicon substrate 40 subjected to the decarbonizing preliminary step in the inert gas atmosphere.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种其表面上形成具有均匀厚度和高绝缘性的SiO 2 SiO 2膜的半导体衬底的制造方法。解决方案：在硅衬底40的表面上形成SiO 2 膜的半导体衬底的制造方法具有SiO 2 膜形成通过使用有机气体的化学气相生长方法在硅衬底40的表面上形成SiO 2 SBS膜44的步骤S4; 通过对经过SiO 2 SBS薄膜形成步骤的硅衬底40进行热处理，通过对其进行热处理来降低SiO 2 SB膜44中的碳密度的脱碳初步步骤S6 惰性气体气氛; 以及通过对在惰性气体气氛中进行脱碳预备步骤的硅衬底40进行热处理，进一步降低SiO 2 SB 44膜中的碳密度的另外的脱碳步骤S8。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2009141055A Method of manufacturing trench gate type semiconductor device 有权
标题翻译：制造闸门型半导体器件的方法
公开(公告)号：JP2009141055A
公开(公告)日：2009-06-25
申请号：JP2007314689
申请日：2007-12-05
申请人： Toyota Motor Corp , トヨタ自動車株式会社
发明人： HISANAGA YUKIHIRO
IPC分类号： H01L29/78 , H01L21/336
摘要： PROBLEM TO BE SOLVED: To suppress inconvenience such as deterioration of gate breakdown voltage and reliability due to film thinning in an insulator.
SOLUTION: A method of manufacturing a trench gate-type semiconductor device where a gate electrode is arranged in a trench part contains a first step of forming the trench part in a semiconductor substrate, a second step of forming a first insulator on a wall face of the trench part, a third step of forming a second insulator to a prescribed depth on an inner side of the first insulator, removing the first insulator to a position deeper than the prescribed depth and forming a depression and a fourth step of forming again the first insulator in a part where the first insulator is removed in the third process.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：抑制由于绝缘体中的膜薄化导致的栅极击穿电压的劣化和可靠性等不便。解决方案：制造沟槽栅型半导体器件的方法，其中栅电极布置在沟槽部分中包含在半导体衬底中形成沟槽部分的第一步骤，在第一步骤中形成第一绝缘体沟槽部分的壁面，第三步骤，在第一绝缘体的内侧上形成规定深度的第二绝缘体，将第一绝缘体移除到比规定深度更深的位置，形成凹陷，形成第四步骤在第三过程中第一绝缘体被去除的部分中再次是第一绝缘体。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2007250912A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2007250912A
公开(公告)日：2007-09-27
申请号：JP2006073527
申请日：2006-03-16
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： SUZUKI TAKASHI , KAWAJI SACHIKO , ISHIKO MASAYASU , SAITO JUN , HISANAGA YUKIHIRO , NAKAGAWA MATSUKO , NISHIWAKI TAKESHI
IPC分类号： H01L29/78 , H01L29/739
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which the electrostatic withstand voltage of a power element is improved.
SOLUTION: A U-MOS 100 in Fig. 1 has an insulating region 50 composed of SiO
2 which has air layers 60 inside and is in contact with an n layer 21e of a superjunction structure 20 inside. The air layers 60 are vertically arranged like windows, and their heights are equal to the total thickness of a semiconductor layer which is arranged on an n
+ substrate 10. A source electrode S is extended in such a manner that it covers the width W
s of the top of the insulating region 50 having the air layers 60 inside. A part of the semiconductor layer 21e in contact with the insulating region 50 around an element formation region is of the same n-type as a channel which is formed by the electric potential of a gate electrode. Accordingly, it has drain electrode potential or collector electrode potential at the time of gate-off, and does not inhibit the formation of a depletion layer at the interface between the n layer 21 acting as a drift and the p layer 30 acting as a body.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种其中功率元件的静电耐受电压提高的半导体器件。解决方案：图1中的U-MOS 100。 1具有由内部具有空气层60并且与内部的超结构结构20的n层21e接触的SiO 2 的绝缘区域50。空气层60像窗口一样垂直布置，并且它们的高度等于布置在n + 衬底10上的半导体层的总厚度。源电极S以这种方式延伸它覆盖了具有内部空气层60的绝缘区域50的顶部的宽度W SB s 。与元件形成区域周围的绝缘区域50接触的半导体层21e的一部分与由栅电极的电位形成的沟道的n型相同。因此，在栅极截止时具有漏极电极电位或集电极电位，并且不抑制作为漂移的n层21与作为主体的p层30之间的界面处的耗尽层的形成。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2010093170A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2010093170A
公开(公告)日：2010-04-22
申请号：JP2008263667
申请日：2008-10-10
申请人： Toyota Motor Corp , トヨタ自動車株式会社
发明人： HISANAGA YUKIHIRO
IPC分类号： H01L21/336 , H01L21/316 , H01L29/78
CPC分类号： H01L21/3105 , H01L21/28211 , H01L29/4236 , H01L29/513 , H01L29/518 , H01L29/66734
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method for sufficiently ensuring an insulation breakdown voltage of a gate oxide film in a method of manufacturing insulated gate type semiconductor devices using a CZ substrate. SOLUTION: A method of manufacturing a semiconductor device includes: a process for forming the gate oxide film 10 containing hydrogen on the surface of the CZ substrate 6 by a plasma CVD method; and a process for heat-treating the gate oxide film 10. By heat-treating the gate oxide film 10, a reduction reaction occurs between hydrogen in the gate oxide film 10 and oxygen deposit defects existing in the CZ substrate 6 near the interface between the gate oxide film 10 and the CZ substrate 6, thus removing the oxygen in the CZ substrate 6, and hence sufficiently ensuring the insulation breakdown voltage of the gate oxide film 10. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造方法，用于在使用CZ衬底制造绝缘栅型半导体器件的方法中充分确保栅极氧化膜的绝缘击穿电压。解决方案：制造半导体器件的方法包括：通过等离子体CVD法在CZ衬底6的表面上形成含有氢的栅极氧化膜10的工艺; 以及对栅极氧化膜10进行热处理的方法。通过对栅极氧化膜10进行热处理，在栅极氧化膜10中的氢和存在于CZ衬底6中的界面附近的氧沉积缺陷之间发生还原反应栅极氧化膜10和CZ基板6，从而去除CZ基板6中的氧，从而充分确保栅极氧化膜10的绝缘击穿电压。版权所有（C）2010，JPO＆INPIT

6. 发明专利

JP2008270365A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008270365A
公开(公告)日：2008-11-06
申请号：JP2007108544
申请日：2007-04-17
申请人： Toyota Motor Corp , トヨタ自動車株式会社
发明人： MIYAGI KYOSUKE , SAITO HIROKAZU , HISANAGA YUKIHIRO
IPC分类号： H01L29/78 , H01L21/336
摘要： PROBLEM TO BE SOLVED: To provide a technique for improving a breakdown voltage in a semiconductor device, where a buried insulator is formed at a deep section in a trench, an insulating layer is formed on the wall surface of a shallow section in the trench, and the inside of the insulating layer is filled with a trench inner conductor.
SOLUTION: The trench T has a shallow trench 30a having width L1, a deep trench 40 having width L2 (L2
摘要翻译：要解决的问题：为了提供一种在沟槽的深部形成埋入式绝缘体的半导体装置中的击穿电压的技术，在浅层的壁部的壁面上形成有绝缘层沟槽，并且绝缘层的内部填充有沟槽内导体。解决方案：沟槽T具有宽度为L1的浅沟槽30a，具有宽度L2（L2

7. 发明专利

JP2007157799A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2007157799A
公开(公告)日：2007-06-21
申请号：JP2005347341
申请日：2005-11-30
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： SUZUKI TAKASHI , KAWAJI SACHIKO , ISHIKO MASAYASU , SAITO JUN , SAITO HIROKAZU , HISANAGA YUKIHIRO
IPC分类号： H01L29/78 , H01L21/336 , H01L21/76 , H01L29/06 , H01L29/739
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device for improving an off withstand voltage by maintaining the charge balance of a peripheral region.
SOLUTION: The semiconductor device 1 has a center region M in which a semiconductor element is formed and the peripheral region N formed at the periphery of the center region. The device comprises a p
- -type body region 28 (impurity low-concentration semiconductor region); an insulating layer 42 that covers the surface side of the body region 28, and an electrically floating conductive member 70 while covering the surface of the insulating layer 42, at the peripheral region N.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过维持周边区域的电荷平衡来提高耐受电压的半导体装置。解决方案：半导体器件1具有其中形成半导体元件的中心区域M和形成在中心区域周边的周边区域N. 该器件包括p 型体区28（杂质低浓度半导体区）; 覆盖体区域28的表面侧的绝缘层42和覆盖绝缘层42的表面的电浮动导电构件70在周边区域N.版权所有（C）2007，JPO＆INPIT

8. 发明专利

JP2010093053A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2010093053A
公开(公告)日：2010-04-22
申请号：JP2008261480
申请日：2008-10-08
申请人： Toyota Motor Corp , トヨタ自動車株式会社
发明人： HISANAGA YUKIHIRO
IPC分类号： H01L29/78 , H01L21/336 , H01L21/76 , H01L29/423 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device for filling a trench with a silicon oxide without forming any seams and without generating any high compressive stress near the trench. SOLUTION: The method of manufacturing the semiconductor device including a structure, where the trench 30 is filled with a silicon oxide 22 includes: a process for forming the trench 30 on the surface of the semiconductor substrate 50; a process for forming a silicon oxide layer 56 on the inner surface of the trench 30 so that a gap 58 is formed at the center of the trench 30; a process for filling the gap 58 with polysilicon 59; and a process for heat-treating a semiconductor substrate 50 under an oxidation atmosphere to change the whole of the filled polysilicon 59 to a silicon oxide. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供一种制造半导体器件的方法，该半导体器件用氧化硅填充沟槽而不形成任何接缝，并且在沟槽附近不产生任何高的压缩应力。解决方案：包括其中填充有氧化硅22的沟槽30的结构的半导体器件的制造方法包括：在半导体衬底50的表面上形成沟槽30的工艺; 在沟槽30的内表面上形成氧化硅层56的工艺，使得在沟槽30的中心形成间隙58; 用多晶硅59填充间隙58的工艺; 以及在氧化气氛下对半导体衬底50进行热处理以将整个填充的多晶硅59改变为氧化硅的工艺。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP2009272550A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2009272550A
公开(公告)日：2009-11-19
申请号：JP2008123618
申请日：2008-05-09
申请人： Toyota Motor Corp , トヨタ自動車株式会社
发明人： SOENO AKITAKA , HISANAGA YUKIHIRO
IPC分类号： H01L21/336 , H01L27/04 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7397 , H01L27/0664 , H01L29/861
摘要： PROBLEM TO BE SOLVED: To provide a reverse conducting type semiconductor device for reducing a recovery loss in a diode element region without increasing an ON voltage in an IGBT element region.
SOLUTION: In the semiconductor device, an IGBT element region J1 and a diode element region J2 are mixed on the same semiconductor substrate. In at least a partial region of a drift layer 60 in the diode element region J2, a low-lifetime region 61 for shortening the lifetime of a hole is formed. The average of the lifetimes of the holes in the drift layer 60 including the low-lifetime region 61 is shorter in the diode element region J2 than in the IGBT element region J1.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于在不增加IGBT元件区域中的导通电压的情况下降低二极管元件区域的恢复损耗的反向导通型半导体器件。解决方案：在半导体器件中，IGBT元件区域J1和二极管元件区域J2混合在同一半导体衬底上。在二极管元件区域J2中的漂移层60的至少一部分区域中，形成用于缩短空穴寿命的低寿命区域61。包括低寿命区域61的漂移层60中的空穴的寿命的平均值在二极管元件区域J2中比在IGBT元件区域J1中更短。版权所有（C）2010，JPO＆INPIT

10. 发明专利

JP2009065010A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2009065010A
公开(公告)日：2009-03-26
申请号：JP2007232415
申请日：2007-09-07
申请人： Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： SUZUKI TAKASHI , ISHIKO MASAYASU , SAITO JUN , NISHIWAKI TAKESHI , HISANAGA YUKIHIRO , IKEDA TOMOHARU
IPC分类号： H01L23/373
CPC分类号： H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device such that its semiconductor substrate can be efficiently cooled. SOLUTION: The semiconductor device 10 has the semiconductor substrate 20 where a semiconductor switching device is formed, a surface electrode 30 provided on the semiconductor substrate 20, and a heat dissipation structure 50 provided on the surface electrode 30. The heat dissipation structure 50 is a complex having a carbon crystal region 52 and a metal region 54. For the carbon crystal region 52, carbon nanotubes, carbon nano-fullerene, diamond, or a combination thereof is used. The heat dissipation structure 50 dissipates heat of the semiconductor substrate 20 from the surface side thereof. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供半导体器件，使得其半导体衬底能够被有效地冷却。解决方案：半导体器件10具有形成半导体开关器件的半导体衬底20，设置在半导体衬底20上的表面电极30和设置在表面电极30上的散热结构50.散热结构 50是具有碳结晶区域52和金属区域54的复合体。对于碳晶体区域52，使用碳纳米管，碳纳米富勒烯，金刚石或其组合。散热结构50从其表面侧散发半导体衬底20的热量。版权所有（C）2009，JPO＆INPIT

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