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1. 发明专利

JP2013053324A Sputtering target and method of manufacturing magnetic memory using the same 有权
标题翻译：溅射目标和使用其制造磁记忆的方法
公开(公告)号：JP2013053324A
公开(公告)日：2013-03-21
申请号：JP2011190868
申请日：2011-09-01
申请人： Toshiba Corp , 株式会社東芝 , Ube Material Industries Ltd , 宇部マテリアルズ株式会社
发明人： KITAGAWA EIJI , DAIBO TATATOMI , NOMA KENJI , KAI TADASHI , YAMAKAWA KOJI , NAGASE TOSHIHIKO , NISHIYAMA KATSUYA , UEDA KOJI , WATANABE DAISUKE , YODA HIROAKI , SANO SATOSHI , NISHIMURA YOSHIHIRO , WATANABE TAKAYUKI , KATO YUZO , UEKI AKIRA
IPC分类号： C23C14/34 , C04B35/053 , C23C14/08 , H01L21/8246 , H01L27/105 , H01L43/10 , H01L43/12
CPC分类号： C23C14/082 , C23C14/3414 , G11C11/161 , H01L27/228 , H01L43/12
摘要： PROBLEM TO BE SOLVED: To provide a sputtering target that can improve an MR ratio of a magnet tunnel junction element, and to provide a method of manufacturing a magnetic memory using the same.SOLUTION: There are provided the sputtering target including a target body 10 that has MgO as a main component and a thickness of 3 mm or smaller, and also the method of manufacturing a magnetic memory using the sputtering target which can improve an MR ratio.
摘要翻译：要解决的问题：提供能够提高磁体隧道结元件的MR比的溅射靶，并提供使用该溅射靶的磁性存储器的制造方法。解决方案：提供了包括具有MgO作为主要成分并且厚度为3mm以下的靶体10的溅射靶，以及使用能够改善MR的溅射靶的磁性存储器的制造方法比。版权所有（C）2013，JPO＆INPIT

2. 发明专利

JP2013137842A Magnetic recording medium and method for manufacturing the same 有权
标题翻译：磁记录介质及其制造方法
公开(公告)号：JP2013137842A
公开(公告)日：2013-07-11
申请号：JP2011287301
申请日：2011-12-28
申请人： Ube Material Industries Ltd , 宇部マテリアルズ株式会社 , National Institute For Materials Science , 独立行政法人物質・材料研究機構
发明人： NISHIMURA YOSHIHIRO , SANO SATOSHI , WATANABE TAKAYUKI , KATO YUZO , TAKAHASHI YUKIKO , BOLLAPRAGADA VARAPRASAD , HONO KAZUHIRO
IPC分类号： G11B5/851 , G11B5/64 , G11B5/65 , G11B5/738
摘要： PROBLEM TO BE SOLVED: To provide a magnetic recording medium in which a FePt magnetic layer is formed on an orientation control layer where DC sputtering is possible, in order to enable mass production thereof, and a method for manufacturing the same.SOLUTION: A method for manufacturing a magnetic recording medium includes a first step of performing DC sputtering of a sputtering target mainly composed of MgO and TiC to form an orientation control layer on a substrate, and a second step of forming a magnetic layer mainly composed of Fe and Pt on the orientation control layer. There is also provided a magnetic recording medium manufactured by the method.
摘要翻译：要解决的问题：为了提供一种磁记录介质，其中在可以进行DC溅射的取向控制层上形成FePt磁性层，以便能够进行大规模生产及其制造方法。方案：一种方法用于制造磁记录介质的步骤包括对主要由MgO和TiC构成的溅射靶进行DC溅射的第一步骤，以在基板上形成取向控制层，以及形成主要由Fe和Pt组成的磁性层的第二步骤取向控制层。还提供了一种通过该方法制造的磁记录介质。

3. 发明专利

JP2013241684A MgO TARGET FOR SPUTTERING 审中-公开
标题翻译： MgO目标用于喷射
公开(公告)号：JP2013241684A
公开(公告)日：2013-12-05
申请号：JP2013186588
申请日：2013-09-09
申请人： Ube Material Industries Ltd , 宇部マテリアルズ株式会社 , Nippon Tungsten Co Ltd , 日本タングステン株式会社
发明人： SANO SATOSHI , NISHIMURA YOSHIHIRO , WATANABE TAKAYUKI , KATO YUZO , UEKI AKIRA , AJITOMI SHINZO , TAKASU MASANOBU , HARA YUSUKE , TANAKA KEISHO
IPC分类号： C23C14/34 , C04B35/04
CPC分类号： H01J37/3429 , C04B35/053 , C04B35/5607 , C04B35/5611 , C04B35/5626 , C04B35/58014 , C04B35/6261 , C04B35/645 , C04B2235/3206 , C04B2235/3839 , C04B2235/3843 , C04B2235/3847 , C04B2235/3886 , C04B2235/5445 , C04B2235/761 , C04B2235/762 , C04B2235/77 , C23C14/081 , C23C14/3407 , C23C14/3414 , G11B5/851 , H01J37/34 , H01J37/3426
摘要： PROBLEM TO BE SOLVED: To provide an MgO target for sputtering, which is capable of increasing a film deposition rate even in cases where MgO is used as a sputtering target when an MgO film is formed.SOLUTION: An MgO target for sputtering is mainly composed of MgO and a conductive substance. The conductive substance is capable of providing a formed MgO film with orientation when the conductive substance is deposited together with MgO by DC sputtering.
摘要翻译：要解决的问题：为了提供一种用于溅射的MgO靶，即使在形成MgO膜时，即使在使用MgO作为溅射靶的情况下也能够提高成膜速度。解决方案：用于溅射的MgO靶主要组成的MgO和导电物质。当通过DC溅射将导电物质与MgO一起沉积时，导电物质能够提供具有取向的形成的MgO膜。

4. 发明专利

JP2013227619A Backing plate and sputtering target 有权
标题翻译：背板和飞溅目标
公开(公告)号：JP2013227619A
公开(公告)日：2013-11-07
申请号：JP2012100231
申请日：2012-04-25
申请人： Nippon Tungsten Co Ltd , 日本タングステン株式会社 , Ube Material Industries Ltd , 宇部マテリアルズ株式会社
发明人： YASUKOCHI RIICHI , AJITOMI SHINZO , BABA TOSHIYUKI , TAKASU MASANOBU , SANO SATOSHI , NISHIMURA YOSHIHIRO , WATANABE TAKAYUKI , KATO YUZO
IPC分类号： C23C14/34
摘要： PROBLEM TO BE SOLVED: To provide: a backing plate preventing plastic deformation and cracks of a sputtering target material as well as peeling off of the sputtering target material; and a sputtering target in which the backing plate is used.SOLUTION: A backing plate 1 to which a sputtering target material 2 is joined has a structure where a second material is filled in continuous open pores of a first material having a skeleton structure including the open pores. The first material has a modulus of longitudinal elasticity higher than the modulus of longitudinal elasticity of the second material. The second material has a thermal conductivity higher than the thermal conductivity of the first material.
摘要翻译：要解决的问题：提供：防止溅射靶材的塑性变形和裂纹以及溅射靶材的剥离的背板; 以及其中使用背板的溅射靶。解决方案：溅射靶材料2接合的背板1具有第二材料填充在具有骨架结构的第一材料的连续开孔中的结构，包括开孔。第一材料具有比第二材料的纵向弹性模量高的纵向弹性模量。第二材料的导热率高于第一材料的导热率。

5. 发明专利

JPH07176193A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH07176193A
公开(公告)日：1995-07-14
申请号：JP31697493
申请日：1993-12-16
申请人： TOSHIBA CORP
发明人： NISHIMURA YOSHIHIRO
IPC分类号： G11C17/00 , G11C16/02 , G11C16/06
摘要： PURPOSE:To enable constitution of one memory cell to be effected with one transistor and to enhance large scale integration processing by erasing data of a memory cell selectively in a byte unit. CONSTITUTION:In erasing operation, a word line WLj to which a memory cell of a byte unit to be erased is connected is started by a row decoder 13 for erasing, and voltage of -5V is selectively applied to a gate of a memory cell Cij being an object. A column gate transistor CG1 which is connected to a bit line BLj to which the memory cell Cij is connected is turned on, voltage of +7V is outputted from an erasing voltage applying circuit 12 through an output node ND1, and voltage of +7V is selectively applied to only the bit line Bj selected by a column decoder. Consequently, erasing voltage of 12V is relatively applied between a gate and a drain of the memory cell Cij being an object, erasing can be performed in a byte unit. Thereby, each memory cell can be constituted with one transistor.

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