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1. 发明专利

JP2013225668A Nonvolatile semiconductor memory device and method of manufacturing the same 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：JP2013225668A
公开(公告)日：2013-10-31
申请号：JP2013055147
申请日：2013-03-18
申请人： Toshiba Corp , 株式会社東芝
发明人： NISHIMURA JUN , YASUTAKE NOBUAKI , SAKAMOTO KEI , OKAMURA TAKAYUKI
IPC分类号： H01L27/105 , H01L45/00 , H01L49/00
CPC分类号： H01L27/2481 , H01L27/2409 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1641 , H01L45/1675
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device that hardly causes degradation and to provide a method of manufacturing the same.SOLUTION: A nonvolatile semiconductor memory device is a semiconductor memory device that includes a cell array layer having first wiring, a memory cell stacked on the first wiring, and second wiring formed on the memory cell so as to cross the first wiring. The memory cell has a current rectifying element and a variable resistance element. In a side wall of the current rectifying element, a portion having an atomic composition ratio of nitrogen higher than that of oxygen exists.
摘要翻译：要解决的问题：提供一种难以引起劣化的非易失性半导体存储器件，并提供其制造方法。解决方案：非易失性半导体存储器件是半导体存储器件，其包括具有第一布线的单元阵列层，存储器电池堆叠在第一布线上，第二布线形成在存储单元上以跨越第一布线。存储单元具有电流整流元件和可变电阻元件。在电流整流元件的侧壁中，存在氮的原子组成比高于氧的原子组成比的部分。

2. 发明专利

JP2011199035A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2011199035A
公开(公告)日：2011-10-06
申请号：JP2010064735
申请日：2010-03-19
申请人： Toshiba Corp , 株式会社東芝
发明人： YASUTAKE NOBUAKI
IPC分类号： H01L27/10 , H01L27/105 , H01L45/00 , H01L49/00
CPC分类号： H01L27/1021 , G11C13/0004 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/1675
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of preventing the diffusion of impurities, such as fluorine and hydrogen, into a memory element without degrading rectification characteristics in a rectifying element.SOLUTION: The semiconductor memory device includes: a conductive wire L2(j) extending in a first direction; a conductive wire L3(i) extending in a second direction crossing the first direction; and a cell unit that is connected in series between the conductive wire L2(j) and the conductive wire L3(i) and is constituted of a variable resistive film or phase change film 17 and a diode including a p-type semiconductor layer and an n-type semiconductor layer. Furthermore, the semiconductor memory device includes: a silicon nitride film 20 formed on a side face of the variable resistive film or phase change film 17; and a silicon oxide film 21 formed on a side face of the diode and having a charge trap less than that in the silicon nitride film 20.
摘要翻译：要解决的问题：提供能够防止诸如氟和氢的杂质扩散到存储元件中的半导体存储器件，而不降低整流元件中的整流特性。解决方案：半导体存储器件包括：导线L2 （j）沿第一方向延伸; 导电线L3（i）沿与第一方向交叉的第二方向延伸; 以及串联连接在导线L2（j）和导线L3（i）之间的电池单元，由可变电阻膜或相变膜17和包括p型半导体层和 n型半导体层。此外，半导体存储器件包括：形成在可变电阻膜或相变膜17的侧面上的氮化硅膜20; 以及形成在二极管的侧面上并且具有比氮化硅膜20小的电荷阱的氧化硅膜21。

3. 发明专利

JP2014010876A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2014010876A
公开(公告)日：2014-01-20
申请号：JP2012148635
申请日：2012-07-02
申请人： Toshiba Corp , 株式会社東芝
发明人： SAKAMOTO KEI , KONDO MASAKI , YASUTAKE NOBUAKI , OKAMURA TAKAYUKI
IPC分类号： G11C13/00 , H01L27/10 , H01L27/105 , H01L45/00 , H01L49/00
CPC分类号： G11C13/0002 , G11C13/004 , G11C13/0069 , G11C2213/72
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of suppressing influence on action due to a memory cell adjacent to a selected memory cell.SOLUTION: A semiconductor memory device according to an embodiment comprises: a plurality of first wiring; a plurality of second wiring; a memory array including memory cells arranged at each intersection part of the first and second wiring; and a control circuit applying a first voltage to selected first wiring, applying a second voltage having a smaller voltage value than that of the first voltage to selected second wiring and applying third and fourth voltages to non-selected first wiring and non-selected second wiring, respectively. The control circuit applies a fifth voltage having a voltage value different from the third voltage only by a first bias voltage value to adjacent non-selected first wiring, which is adjacent to the selected first wiring, among the non-selected first wiring and applies a sixth voltage having a voltage value different from the fourth voltage only by a second bias voltage value to adjacent non-selected second wiring, which is adjacent to the selected second wiring, among the non-selected second wiring.
摘要翻译：要解决的问题：提供一种能够抑制由于与所选存储单元相邻的存储单元而引起的动作的影响的半导体存储器件。解决方案：根据实施例的半导体存储器件包括：多个第一布线; 多个第二布线; 包括布置在第一和第二布线的每个交叉部分处的存储单元的存储器阵列; 以及控制电路，对所选择的第一布线施加第一电压，向所选择的第二布线施加具有比所述第一电压小的电压值的第二电压，并将第三和第四电压施加到未选择的第一布线和未选择的第二布线，分别。控制电路在未选择的第一布线中将与第三电压不同的电压值的第五电压施加到与所选择的第一布线相邻的相邻未选择的第一布线的第一偏置电压值，在未选择的第二布线中，具有与第四电压不同的电压值与第二偏置电压值相邻的未选择第二布线的第六电压。

4. 发明专利

JP2013004541A Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：JP2013004541A
公开(公告)日：2013-01-07
申请号：JP2011130662
申请日：2011-06-10
申请人： Toshiba Corp , 株式会社東芝
发明人： NISHIMURA JUN , YASUTAKE NOBUAKI , OKAMURA TAKAYUKI
IPC分类号： H01L27/105 , G11C13/00 , H01L21/329 , H01L29/861 , H01L29/866 , H01L29/868 , H01L45/00 , H01L49/00
CPC分类号： H01L27/1021 , H01L27/2409 , H01L27/2481 , H01L29/868 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： PROBLEM TO BE SOLVED: To enable reduction in voltage.SOLUTION: A semiconductor storage element of an embodiment comprises a cell array layer including first wiring, memory cells laminated on the first wiring, and second wiring formed on the memory cells so as to intersect with the first wiring. The memory cell includes a variable resistive element with a memory cell electrically rewritable by application of an electric signal having a different polarity and a current control element flowing a bidirectional current to the variable resistive element, which are series connected. The current control element has an i-type semiconductor and semiconductors of first and second conductivity types contacting both sides of the i-type semiconductor. A diffusion length of a second impurity in the second conductivity type semiconductor is longer than a diffusion length of a first impurity in the first conductivity type semiconductor. In a junction of the first conductivity type semiconductor and the i-type semiconductor, an impact ionization promotion part is formed which promotes generation of impact ions to a higher degree than in a junction of the second conductivity type semiconductor and the i-type semiconductor.
摘要翻译：要解决的问题：能够降低电压。解决方案：实施例的半导体存储元件包括包括第一布线的单元阵列层，层叠在第一布线上的存储单元，以及形成在存储单元上以与第一布线相交的第二布线。存储单元包括可变电阻元件，其具有通过施加具有不同极性的电信号而电可重写的存储单元，以及将双向电流流向可串联连接的可变电阻元件的电流控制元件。电流控制元件具有i型半导体和接触i型半导体两侧的第一和第二导电类型的半导体。第二导电型半导体中的第二杂质的扩散长度比第一导电型半导体中的第一杂质的扩散长度长。在第一导电型半导体和i型半导体的接合部中，形成有冲击离子化促进部，其比第二导电型半导体和i型半导体的接合部更高程度地促进冲击离子的产生。版权所有（C）2013，JPO＆INPIT

5. 发明专利

JP2012129286A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2012129286A
公开(公告)日：2012-07-05
申请号：JP2010277962
申请日：2010-12-14
申请人： Toshiba Corp , 株式会社東芝
发明人： YASUTAKE NOBUAKI
IPC分类号： H01L27/105 , G11C13/00 , H01L21/28
CPC分类号： H01L45/1253 , H01L27/2409 , H01L27/2481
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device with suppressed degradation of memory cell characteristics.SOLUTION: A memory cell comprises a diode layer, a variable resistor layer, and an electrode layer. The diode layer serves as a rectifying element. The variable resistor layer serves as a variable resistive element. The electrode layer is provided between the variable resistor layer and the diode layer, and is formed so as to contact the variable resistor layer and the diode layer. The electrode layer includes a titanium nitride layer composed of titanium nitride. When the ratio of titanium elements to nitride elements in a first region in the titanium nitride layer is a first ratio, the ratio of titanium elements to nitride elements in a second region, which is in the titanium nitride layer and is closer to the variable resistor layer than to the first region, is a second ratio, the second ratio is larger than the first ratio.
摘要翻译：要解决的问题：提供具有抑制的存储单元特性劣化的半导体存储器件。解决方案：存储单元包括二极管层，可变电阻层和电极层。二极管层用作整流元件。可变电阻层用作可变电阻元件。电极层设置在可变电阻层和二极管层之间，形成为与可变电阻层和二极管层接触。电极层包括由氮化钛构成的氮化钛层。当氮化钛层的第一区域中的钛元素与氮化物元素的比率是第一比率时，在氮化钛层中的第二区域中的钛元素与氮化物元素的比例更接近可变电阻器层比第一区域高，为第二比例，第二比例大于第一比例。版权所有（C）2012，JPO＆INPIT

6. 发明专利

JP2010219152A Semiconductor apparatus and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：JP2010219152A
公开(公告)日：2010-09-30
申请号：JP2009061717
申请日：2009-03-13
申请人： Toshiba Corp , 株式会社東芝
发明人： YASUTAKE NOBUAKI
IPC分类号： H01L29/78 , H01L21/336 , H01L29/786
CPC分类号： H01L29/7833 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor apparatus having a source-drain region in which a semiconductor layer that generates sufficient distortion in a channel region is buried, without reducing short channel characteristics, and to provide a method of manufacturing the same. SOLUTION: A semiconductor apparatus includes: a gate electrode 13 formed on a main surface of an N-type silicon substrate 11 via a gate insulation film; source/drain regions 17a and 17b having a structure in which first semiconductor layers 15a and 15b formed so as to sandwich a channel region 14 formed below the gate electrode 13, and which includes germanium for giving distortion to the channel region 14 and carbon for suppressing P-type impurity boron and diffusion of boron, and second semiconductor layers 16a and 16b containing germanium and boron, are laminated in this order; and extension regions 18a and 18b adjacent to the channel region 14 from the side surface of the gate electrode 13 of the second semiconductor layers 16a and 16b. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供一种具有源极 - 漏极区域的半导体器件，其中在沟道区域中产生足够的畸变的半导体层被掩埋，而不减少短沟道特性，并提供其制造方法。解决方案：半导体装置包括：栅电极13，其经由栅极绝缘膜形成在N型硅基板11的主表面上; 源极/漏极区域17a和17b具有这样的结构，其中形成第一半导体层15a和15b以形成在栅电极13下方形成的沟道区域14，并且包括用于使沟道区域14变形的锗和用于抑制 P型杂质硼和硼的扩散以及含有锗和硼的第二半导体层16a和16b按顺序层压; 以及从第二半导体层16a，16b的栅电极13的侧面与沟道区域14相邻的延伸区域18a，18b。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2011199197A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2011199197A
公开(公告)日：2011-10-06
申请号：JP2010066945
申请日：2010-03-23
申请人： Toshiba Corp , 株式会社東芝
发明人： NISHIMURA JUN , YASUTAKE NOBUAKI , MURATA TAKESHI
IPC分类号： H01L27/10 , H01L27/105 , H01L45/00 , H01L49/00
CPC分类号： H01L27/2409 , G11C13/0004 , H01L27/2463 , H01L27/2481 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device that suppress an influence of a fixed charge in an interlayer film formed between memory cells on a rectifier element, and further prevent wiring and electrodes from oxidizing.SOLUTION: The semiconductor memory device includes a bit line BL extending in a first direction, word lines WL extending in a second direction crossing the first direction, diodes DI connected between the bit line BL and word lines WL, switching elements SW connected in series with the diodes DI between the bit line BL and word lines WL, first side wall films formed on side faces of the diodes DI, and second side wall films formed on side faces of at least one of the bit line BL and word lines WL and differing from the first side wall films in at least one of the film type and film thickness.
摘要翻译：要解决的问题：提供一种半导体存储器件，其抑制在整流元件上的存储单元之间形成的层间膜中的固定电荷的影响，并且进一步防止布线和电极氧化。解决方案：半导体存储器件包括位线BL沿第一方向延伸，在与第一方向交叉的第二方向上延伸的字线WL，连接在位线BL和字线WL之间的二极管DI，与位线BL和位线BL之间的二极管DI串联连接的开关元件SW 字线WL，形成在二极管DI的侧面上的第一侧壁膜和形成在位线BL和字线WL中的至少一个的侧面上的第二侧壁膜，并且至少与第一侧壁膜不同胶片类型和胶片厚度之一。

8. 发明专利

JP2009105163A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2009105163A
公开(公告)日：2009-05-14
申请号：JP2007274302
申请日：2007-10-22
申请人： Toshiba Corp , 株式会社東芝
发明人： KUSUNOKI NAOKI , YASUTAKE NOBUAKI
IPC分类号： H01L29/78 , H01L21/8238 , H01L27/092
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having high carrier mobility in a channel region.
SOLUTION: The semiconductor device 1 is provided with a semiconductor substrate 2, a semiconductor layer 3 which is formed on the semiconductor substrate and is formed of first crystal whose inner carrier mobility is higher than a Si crystal, a gate insulting film 4 formed on the semiconductor layer, a gate electrode formed on the gate insulating film and source/drain regions which are formed by sandwiching the semiconductor layer, include second crystal giving distortion to the semiconductor layer in a direction where carrier mobility in the semiconductor layer rises and have source/drain extension regions being shallow regions which are brought into contact with the semiconductor layer.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供在沟道区域中具有高载流子迁移率的半导体器件。解决方案：半导体器件1设置有半导体衬底2，形成在半导体衬底上并由内部载流子迁移率高于Si晶体的第一晶体形成的半导体层3，栅极绝缘膜4 形成在半导体层上的形成在栅极绝缘膜上的栅极电极和通过夹持半导体层形成的源极/漏极区域包括在半导体层中的载流子迁移率上升的方向上向半导体层施加失真的第二晶体，源极/漏极延伸区域是与半导体层接触的浅区域。版权所有（C）2009，JPO＆INPIT

9. 发明专利

JP2006332337A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006332337A
公开(公告)日：2006-12-07
申请号：JP2005153948
申请日：2005-05-26
申请人： Toshiba Corp , 株式会社東芝
发明人： YASUTAKE NOBUAKI
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/417
CPC分类号： H01L21/823814 , H01L21/823807 , H01L29/7848
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device realizing high speed operation and its manufacturing method.
SOLUTION: The semiconductor device solving the problem includes: a gate electrode formed on a first conductive type region of a semiconductor substrate via an insulation film; a first sidewall formed on the side face of the gate electrode; a second sidewall formed on the side face of the first sidewall; a semiconductor layer formed below the second sidewall containing a first impurity layer of a second conductivity type and containing germanium; a second impurity layer formed in a region outside the sidewall of the second sidewall and containing more impurities of a second conductivity type than the first impurity layer; and a silicide layer formed on the second impurity layer.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供实现高速运转的半导体装置及其制造方法。解决方案：解决该问题的半导体器件包括：通过绝缘膜形成在半导体衬底的第一导电类型区域上的栅电极; 形成在所述栅电极的侧面上的第一侧壁; 形成在第一侧壁的侧面上的第二侧壁; 形成在所述第二侧壁下方的半导体层，所述半导体层包含第二导电类型的第一杂质层并且含有锗; 形成在所述第二侧壁的所述侧壁外侧的区域中并且包含比所述第一杂质层更多的第二导电类型的杂质的第二杂质层; 以及形成在第二杂质层上的硅化物层。版权所有（C）2007，JPO＆INPIT

10. 发明专利

JP2005217245A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005217245A
公开(公告)日：2005-08-11
申请号：JP2004022912
申请日：2004-01-30
申请人： Toshiba Corp , 株式会社東芝
发明人： YASUTAKE NOBUAKI
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L29/6653 , H01L21/2807 , H01L21/28114 , H01L29/42376 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： PROBLEM TO BE SOLVED: To solve the problem that short circuit is caused between a gate electrode and a source/drain region due to fining of the gate electrode of an MOSFET with a raised source/drain structure.
SOLUTION: The semiconductor device is an MOSFET having the raised source/drain structure formed on a silicon substrate 10. It has a three-layer structure consisting of a first nitride film 16, an oxide film 17 and a second nitride film 18 in an upper side surface of the gate electrode 20. The lower side surface of the gate electrode has a gate side wall insulating film having a two-layer structure consisting of the oxide film 17 and the second nitride film 18, and a raised source/drain region consisting of an impurity region selectively formed in the surface of the silicon substrate and an impurity region formed from the surface thereof.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了解决由于具有升高的源极/漏极结构的MOSFET的栅电极的精细化而在栅电极和源极/漏极区之间引起的短路的问题。解决方案：半导体器件是在硅衬底10上形成有升高的源极/漏极结构的MOSFET。它具有由第一氮化物膜16，氧化物膜17和第二氮化物膜18组成的三层结构栅极电极20的上侧表面。栅电极的下侧表面具有由氧化物膜17和第二氮化物膜18组成的两层结构的栅极侧壁绝缘膜，以及升高的源极/ 漏极区域由选择性地形成在硅衬底的表面中的杂质区域和由其表面形成的杂质区域组成。版权所有（C）2005，JPO＆NCIPI

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