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    • 1. 发明专利
    • Semiconductor integrated circuit
    • 半导体集成电路
    • JP2011029333A
    • 2011-02-10
    • JP2009172358
    • 2009-07-23
    • Toshiba Corp株式会社東芝
    • YAMAGUCHI HIROYUKI
    • H01L21/822H01L27/04
    • PROBLEM TO BE SOLVED: To provide an LSI having a power cut-off circuit cell, capable of controlling the turning off and on of a power supply to some layout blocks among a plurality of layout blocks according to a need, thus suppressing the deterioration in efficiency of wiring and an increase in an power supply area and in a chip size.
      SOLUTION: A semiconductor integrated circuit includes a plurality of layout blocks 11 and 12 in a chip, a power cut-off analog switch 13 which cuts off a power supply supplying power to some layout blocks among the plurality of layout blocks when necessary, and a circuit cut-off isolation cell 14 interposed between an output node of a power cut-off block 12 to be cut off power supply and a constantly powered block 11 not cut off power supply. The semiconductor integrated circuit is provided with a power cut-off circuit cell 20 having the power cut-off analog switch and the circuit cut-off isolation cell incorporated therein.
      COPYRIGHT: (C)2011,JPO&INPIT
    • 要解决的问题:为了提供具有断电电路单元的LSI,能够根据需要控制多个布局块中的某些布局块的电源的接通和导通,从而抑制 布线效率的恶化以及电源面积和芯片尺寸的增加。 解决方案:半导体集成电路包括芯片中的多个布局块11和12,功率截止模拟开关13,当需要时切断向多个布局块中的某些布局块供电的电源 以及插入在切断电源的断电块12的输出节点和未切断电源的不断供电的块11之间的电路截止隔离单元14。 半导体集成电路设置有具有断电模拟开关和电路截止隔离单元的断电电路单元20。 版权所有(C)2011,JPO&INPIT
    • 4. 发明专利
    • Semiconductor device
    • 半导体器件
    • JP2008270612A
    • 2008-11-06
    • JP2007113244
    • 2007-04-23
    • Toshiba Corp株式会社東芝
    • YAMAGUCHI HIROYUKIWATANABE KOICHIWAKIYAMA TOSHIJIURAYAMA ATSUSHIICHIDA MAKOTO
    • H01L21/768
    • PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device capable of reducing the occurrence of a via-defect such as high resistance in a plasma etching step for forming a hole conducting to floating lower-layer metal wiring.
      SOLUTION: A dummy via 1 is formed on lower-layer wiring 101 connected with upper-layer wiring 201 by a via 301, and a dummy via 2 is formed on lower-layer wiring 102 connected with the upper-layer wiring 201 by a via 302. Upper surfaces of vias are covered with dummy wiring 1A, 2A of the upper-layer wiring so as not to expose upper surfaces of these dummy vias. When performing plasma etching using these dummy vias, the effect of charges accumulated on lower-layer wiring is distributed.
      COPYRIGHT: (C)2009,JPO&INPIT
    • 要解决的问题:提供一种制造半导体器件的方法,该半导体器件能够减少用于形成对浮动下层金属布线导通的空穴的等离子体蚀刻步骤中的诸如高电阻的通孔缺陷的发生。 解决方案:通孔301通过通孔301形成在与上层布线201连接的下层布线101上的虚设通孔1,并且在与上层布线201连接的下层布线102上形成虚设通孔2 通孔302的上表面被上层布线的虚设布线1A,2A覆盖,以便不露出这些虚拟通孔的上表面。 当使用这些虚拟通孔进行等离子体蚀刻时,分散积累在下层布线上的电荷的影响。 版权所有(C)2009,JPO&INPIT
    • 6. 发明专利
    • Metal pattern generating method and generating apparatus
    • 金属图案生成方法和生成装置
    • JP2009027084A
    • 2009-02-05
    • JP2007190801
    • 2007-07-23
    • Toshiba Corp株式会社東芝
    • WAKIYAMA TOSHIJIYAMAGUCHI HIROYUKIHERAI TSUTOMUICHIDA MAKOTOWATANABE KOICHIOKANO HIROKAZUURAYAMA ATSUSHI
    • H01L21/82G06F17/50
    • PROBLEM TO BE SOLVED: To provide a metal pattern generating method and generating apparatus capable of shortening the time required for generating a metal pattern including a dummy metal.
      SOLUTION: The metal pattern generating method has: a step of reading cell arrangement data and setting a region where wiring is possible ; a step of arranging the rectangular pattern of a prescribed dimension in a matrix shape at the grid point of a wiring grid for layout design on the entire surface of the region where wiring is possible; a step of arranging a wiring pattern for signal wiring and for power wiring on the wiring grid of the region where wiring is possible; and a step of generating the metal pattern by combining the generated rectangular pattern and wiring pattern.
      COPYRIGHT: (C)2009,JPO&INPIT
    • 解决的问题:提供能够缩短生成包括虚拟金属的金属图案所需的时间的金属图案生成方法和发生装置。 解决方案:金属图案生成方法具有:读取单元布置数据并设置可能布线的区域的步骤; 在布线设计的布线栅格的网格点处,在可能布线的区域的整个表面上布置具有矩形形状的规定尺寸的矩形图案的步骤; 在可能布线的区域的布线栅格上布置用于信号布线和电力布线的布线图案的步骤; 以及通过组合所生成的矩形图案和布线图案来生成金属图案的步骤。 版权所有(C)2009,JPO&INPIT
    • 9. 发明专利
    • AUTOMATIC TRANSACTION MACHINE
    • JPH0212495A
    • 1990-01-17
    • JP16085988
    • 1988-06-30
    • TOSHIBA CORP
    • YAMAGUCHI HIROYUKI
    • G07D9/00
    • PURPOSE:To prevent declines in the operating efficiency of transaction processes and the service to customers by writing information related to transactions of delivered and received amounts in the storing section of a reading medium when no information related to transactions of delivered and received amounts is read from the storing section of the reading medium. CONSTITUTION:This automatic transaction machine is provided with a main controlling section 161, card reading section 162, receipt issuing section 163, and bankbook reading and printing section 164. A storing section 165 stores programs of operations of an information reading means and information writing means, transaction data of delivered and received amounts, etc., in prescribed addresses. When no information related to transactions of delivered and received amounts is read form the storing section 165 of a reading medium provided with the section 165 storing information related transactions of delivered and received amounts, information is requested to a central station, for example, a host computer. When the host computer transmits information related to transactions of delivered and received amounts, the information is written in the storing section 165. Therefore, a decline in the operating efficiency of transaction processes can be prevented.