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    • 1. 发明专利
    • Method of placement and routing for semiconductor integrated circuit device
    • 半导体集成电路器件的放置和布线方法
    • JP2009038240A
    • 2009-02-19
    • JP2007201943
    • 2007-08-02
    • Toshiba CorpToshiba Digital Media Engineering Corp東芝デジタルメディアエンジニアリング株式会社株式会社東芝
    • SHIBATA YUKIHIKOTOMONO MASAYACHIGIRA TAKASHI
    • H01L21/82G06F17/50H01L21/822H01L27/04
    • PROBLEM TO BE SOLVED: To simultaneously resolve the problems of non-wire connection of signal wirings, non-achievement of timing or the like and voltage drop in power supply line.
      SOLUTION: The method of placement and routing for semiconductor integrated circuit device includes a power supply wiring step (ST12) wherein the power supply wiring is wired so that the power supply for cell arranged based on a net list is supplied through at least two or more of different routes, a cell arrangement step (ST13) wherein a plurality of cells are arranged, a signal wiring step (ST14) wherein the signal wiring between cells arranged in the ST13 on the wiring layer same as the initial power supply wiring wired in the ST12, and a wiring correction step (ST15) wherein the initial power supply wiring arranged near the troubled signal wiring is removed within a range of allowable voltage drop and the troubled signal wiring is rewired when the non-wire connections of signal wiring or wiring short-circuit arises in the ST14 or violation of timing arises in the signal wiring.
      COPYRIGHT: (C)2009,JPO&INPIT
    • 要解决的问题:同时解决信号布线的无线连接,不达成定时等问题,以及供电线路中的电压降。 解决方案:半导体集成电路器件的放置和布线方法包括:电源布线步骤(ST12),其中电源布线被布线,使得基于网络列表布置的单元格的电源至少提供 两条或多条不同的路径,其中布置多个单元的单元布置步骤(ST13),布置在布线层上的ST13中的单元之间的信号布线与初始电源布线相同的信号布线步骤(ST14) 布线校正步骤(ST15),其中布置在故障信号布线附近的初始电源布线在允许的电压降范围内被去除,并且当信号布线的非线连接时,故障信号布线被重新布线 或在ST14中出现布线短路,或信号布线中出现违规。 版权所有(C)2009,JPO&INPIT
    • 2. 发明专利
    • Method of designing semiconductor integrated circuit
    • 设计半导体集成电路的方法
    • JP2010141005A
    • 2010-06-24
    • JP2008314290
    • 2008-12-10
    • Toshiba Corp株式会社東芝
    • ISHIMOTO SHINJITOMONO MASAYA
    • H01L21/82G06F17/50H01L27/118
    • PROBLEM TO BE SOLVED: To provide a method of designing a semiconductor integrated circuit increasing the degree of freedom in design change after arranging and interconnecting of the semiconductor integrated circuit to improve performance.
      SOLUTION: The method includes an arranging and interconnecting step S1 of arranging and interconnecting a standard cell, a timing analysis step S2 of performing timing analysis on arranging and interconnecting data obtained at the standard cell arranging and interconnecting step S1, a gate array cell insertion step S3 of inserting a gate array cell into a path including a violation on the arranging and interconnecting data based on a result obtained at the timing analysis step S2, replacement standard cell extracting steps (S5-S8) of extracting a replacement standard cell which is logically equivalent to the gate array cell from the arranging and interconnecting data when another violation occurs in the violation-including path by inserting the gate array cell, and a standard cell replacing step S9 of replacing the gate array cell with the replacement standard cell due to design change of a wiring layer.
      COPYRIGHT: (C)2010,JPO&INPIT
    • 要解决的问题:提供一种设计半导体集成电路的方法,其在布置和互连半导体集成电路之后提高设计变化的自由度以提高性能。 解决方案:该方法包括布置和互连标准单元的布置和互连步骤S1,对在标准单元布置和互连步骤S1获得的数据进行布置和互连的时序分析的时序分析步骤S2,门阵列 基于在定时分析步骤S2获得的结果,将门阵列单元插入到布置和互连数据的路径的路径中的单元插入步骤S3,提取替换标准单元的替换标准单元提取步骤(S5-S8) 当通过插入门阵列单元在违反包含路径中发生另一次冲突时,逻辑上等同于门阵列单元的阵列单元;以及用替换标准单元替换门阵列单元的标准单元替换步骤S9 由于布线层的设计变化。 版权所有(C)2010,JPO&INPIT