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1. 发明专利

JP2009038240A Method of placement and routing for semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路器件的放置和布线方法
公开(公告)号：JP2009038240A
公开(公告)日：2009-02-19
申请号：JP2007201943
申请日：2007-08-02
申请人： Toshiba Corp , Toshiba Digital Media Engineering Corp , 東芝デジタルメディアエンジニアリング株式会社 , 株式会社東芝
发明人： SHIBATA YUKIHIKO , TOMONO MASAYA , CHIGIRA TAKASHI
IPC分类号： H01L21/82 , G06F17/50 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To simultaneously resolve the problems of non-wire connection of signal wirings, non-achievement of timing or the like and voltage drop in power supply line.
SOLUTION: The method of placement and routing for semiconductor integrated circuit device includes a power supply wiring step (ST12) wherein the power supply wiring is wired so that the power supply for cell arranged based on a net list is supplied through at least two or more of different routes, a cell arrangement step (ST13) wherein a plurality of cells are arranged, a signal wiring step (ST14) wherein the signal wiring between cells arranged in the ST13 on the wiring layer same as the initial power supply wiring wired in the ST12, and a wiring correction step (ST15) wherein the initial power supply wiring arranged near the troubled signal wiring is removed within a range of allowable voltage drop and the troubled signal wiring is rewired when the non-wire connections of signal wiring or wiring short-circuit arises in the ST14 or violation of timing arises in the signal wiring.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：同时解决信号布线的无线连接，不达成定时等问题，以及供电线路中的电压降。解决方案：半导体集成电路器件的放置和布线方法包括：电源布线步骤（ST12），其中电源布线被布线，使得基于网络列表布置的单元格的电源至少提供两条或多条不同的路径，其中布置多个单元的单元布置步骤（ST13），布置在布线层上的ST13中的单元之间的信号布线与初始电源布线相同的信号布线步骤（ST14）布线校正步骤（ST15），其中布置在故障信号布线附近的初始电源布线在允许的电压降范围内被去除，并且当信号布线的非线连接时，故障信号布线被重新布线或在ST14中出现布线短路，或信号布线中出现违规。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2007207906A Semiconductor integrated circuit and method for manufacturing the same 审中-公开
标题翻译：半导体集成电路及其制造方法
公开(公告)号：JP2007207906A
公开(公告)日：2007-08-16
申请号：JP2006023201
申请日：2006-01-31
申请人： Toshiba Corp , Toshiba Digital Media Engineering Corp , 東芝デジタルメディアエンジニアリング株式会社 , 株式会社東芝
发明人： CHIGIRA TAKASHI , ICHIDA MAKOTO
IPC分类号： H01L21/60 , H01L21/822 , H01L25/04 , H01L25/18 , H01L27/04
CPC分类号： H01L2224/48091 , H01L2224/73265 , H01L2924/30107 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit in which in a multi-chip mounting for forming an SiP, semiconductor chips can be connected to one another at a low cost and by a method having favorable production efficiency without degrading performance, and to provide a method for manufacturing the semiconductor integrated circuit.
SOLUTION: A recess 13 for forming a side face pad is formed on a dicing line 11. Thereafter, an anti-diffusion layer 14 is formed without affecting an element characteristic of the semiconductor integrated circuit. The recess 13 is embedded with a conductor material 15. Upon separation as a chip in a dicing process, a pad is formed on the side face of the chip. The semiconductor integrated circuit chips thus formed are adjacent to one another and the conductor material 15 of the side face pad is heated and dissolved for jointing.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种半导体集成电路，其中在用于形成SiP的多芯片安装中，半导体芯片可以以低成本彼此连接，并且通过具有良好生产效率的方法而不降低性能并且提供一种用于制造半导体集成电路的方法。解决方案：在切割线11上形成用于形成侧面焊盘的凹部13.此后，形成抗扩散层14，而不影响半导体集成电路的元件特性。凹部13内嵌有导体材料15.作为切片处理中的芯片分离，在芯片的侧面形成有焊盘。这样形成的半导体集成电路芯片彼此相邻，并且侧面焊盘的导体材料15被加热并溶解以进行接合。版权所有（C）2007，JPO＆INPIT

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