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1. 发明专利

JP2007281136A Semiconductor substrate, and substrate inspection method 审中-公开
标题翻译：半导体基板和基板检查方法
公开(公告)号：JP2007281136A
公开(公告)日：2007-10-25
申请号：JP2006104289
申请日：2006-04-05
申请人： Toshiba Corp , 株式会社東芝
发明人： HAYASHI HIROYUKI , NAGAI TAKAMITSU , NODA TOMONOBU , KADOTA KENICHI , OZAKI HISASHIRO
IPC分类号： H01L21/66 , H01J37/28
CPC分类号： H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To quickly and easily inspect a defective semiconductor substrate having a short-circuit between contact wires. SOLUTION: An electric potential contrast image is acquired from a semiconductor substrate S comprising a TEG including contact wires CW alternately and repetitively formed so that one of the adjacent contact wires CW is grounded to a P well 2, and the other of the adjacent contact wires CW is insulated from the P well 2, and whether it is non-defective or defective is judged by the difference in light and darkness in the acquired image. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了快速且容易地检查在接触线之间具有短路的缺陷半导体衬底。解决方案：从包括接触线CW的TEG的半导体衬底S交替重复地形成电位对比图像，使得相邻的接触线CW中的一个接地到P阱2，另一个相邻的接触线CW与P阱2绝缘，并且通过所获取的图像中的亮度和黑暗的差异来判断是否是无缺陷或有缺陷的。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2006017744A Defect inspection recipe creating method 审中-公开
标题翻译：缺陷检查协议创建方法
公开(公告)号：JP2006017744A
公开(公告)日：2006-01-19
申请号：JP2005267313
申请日：2005-09-14
申请人： Toshiba Corp , 株式会社東芝
发明人： NODA TOMONOBU
IPC分类号： G01N21/956 , G01N23/225 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To provide a method for creating an optimum defect inspection recipe capable of detecting all defect species independent of the degree of a creators's skill.
SOLUTION: A provisional inspection recipe is created through the use of a simulated defective wafer 1 provided with simulated defect patterns DF1-DF3 having changes in a height direction and changes in a planar shape to a simulated normal pattern. Defect inspection is performed on the simulated defective wafer 1. Detected defect data is collated with previously acquired simulated defect data of the simulated defective wafer 1 to quantify defect detection sensitivity. A recipe parameter is changed until a desired defect detection rate is acquired to create a provisional inspection recipe.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种创建能够独立于创造者技能程度来检测所有缺陷种类的最佳缺陷检查配方的方法。解决方案：通过使用具有模拟缺陷图案DF1-DF3的模拟缺陷晶片1创建临时检查配方，所述模拟缺陷晶片1具有在高度方向上的变化并且将平面形状改变为模拟法线图案。对模拟的缺陷晶片1执行缺陷检查。检测到的缺陷数据与先前获取的模拟缺陷晶片1的模拟缺陷数据进行比较，以量化缺陷检测灵敏度。更改配方参数直到获取所需的缺陷检测率以创建临时检查配方。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2005251925A System and method for production device control and program 有权
标题翻译：用于生产设备控制和程序的系统和方法
公开(公告)号：JP2005251925A
公开(公告)日：2005-09-15
申请号：JP2004059175
申请日：2004-03-03
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUSHITA HIROSHI , NODA TOMONOBU , KADOTA KENICHI , SUGAMOTO JIYUNJI , USHIKU YUKIHIRO
IPC分类号： H01L21/66 , G01R31/26 , H01L21/02 , H01L23/58
CPC分类号： H01L22/20 , G01R31/2894 , G05B23/0248 , G05B2219/31357 , Y02P90/14
摘要： PROBLEM TO BE SOLVED: To provide a production device control system capable of specifying device parameters to clear source of defective troubles. SOLUTION: This system comprises a production information input part 40 obtaining time-series data of the device parameters controlling a plurality of production devices 2a to 2n, respectively, a failure pattern classifying part 42 for classifying wafer in-plane distribution trends of defective semiconductor devices on a wafer manufactured by the plurality of production devices 2a to 2n, a feature value calculator 44 for statistically processing respective time-series data by a plurality of algorithms to calculate a plurality of feature values corresponding to each of the plurality of algorithms, a feature value analyzer 46 for calculating a frequency distribution of the feature value corresponding to each of presence of a defective pattern with regard to each of the plurality of feature values to execute a significant test between the frequency distributions according to the presence of the defective pattern, and an abnormality parameter extractor 48 for comparing a test value calculated by the significant test with a test reference value to extract an occurrence cause feature value of the defective pattern. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供能够指定设备参数以清除缺陷故障源的生产设备控制系统。解决方案：该系统包括生产信息输入部分40，分别获得控制多个生产装置2a至2n的装置参数的时间序列数据;故障模式分类部分42，用于将晶片的平面内分布趋势进行分类; 由多个生产装置2a至2n制造的晶片上的有缺陷的半导体器件，特征值计算器44，用于通过多个算法对各个时间序列数据进行统计处理，以计算与多个算法中的每一个对应的多个特征值，特征值分析器46，用于计算与多个特征值中的每个特征值相关的每个存在缺陷图案的特征值的频率分布，以根据有缺陷的存在来执行频率分布之间的有效测试模式，以及用于比较测试值计算的异常参数提取器48 通过具有测试参考值的显着测试来提取出现故障模式的特征值。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2003066590A Mask pattern evaluating system and method for the same 有权
标题翻译：掩模图案评估系统及其方法
公开(公告)号：JP2003066590A
公开(公告)日：2003-03-05
申请号：JP2001253110
申请日：2001-08-23
申请人： Toshiba Corp , 株式会社東芝
发明人： NODA TOMONOBU
IPC分类号： G03F1/84 , G03F1/08
CPC分类号： G03F1/84
摘要： PROBLEM TO BE SOLVED: To make mask patterns able to be more exactly evaluated by taking the acceptance or rejection of a pattern relief into consideration in evaluating the mask patterns.
SOLUTION: This system has a pattern image acquiring section 112 which acquires the pattern images of the mask patterns, a program defect generating section 113 to which the sizes and number of pieces of the defects generated by particles are inputted and spuriously generates the defects in accordance with the sizes and number of pieces of the defects, a pattern defect image forming section 115 which composites the generated spurious defects with the acquired pattern images, a pattern relief deciding section 117 which decides the acceptance or rejection of the pattern relief in accordance with a pattern relief rule 116 with respect to the spurious defects in the formed pattern defect images and a pattern relief rejection rate calculating section 118 which calculates a pattern relief rejection rate or a pattern relief rate in accordance with the results of the pattern relief deciding section 117.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：通过在评估掩模图案时考虑到图案浮雕的接受或拒绝，使掩模图案能够被更准确地评估。解决方案：该系统具有获取掩模图案的图案图像的图案图像获取部件112，输入由粒子生成的缺陷的尺寸和数量的程序缺陷产生部件113，并根据该错误产生缺陷具有缺陷的尺寸和数量的图案缺陷图像形成部115，其将所产生的杂散缺陷与所获取的图案图像复合，图案解除判定部117，其根据图案形状判定部117决定图案浮雕的接受或拒绝图形消除规则116相对于形成的图案缺陷图像中的虚假缺陷，以及图案排除废除率计算部118，其根据图案解除判定部117的结果计算图案排除率或图案缓解率。

5. 发明专利

JP2001085482A DEVICE AND METHOD FOR SEMICONDUCTOR INSPECTION 失效
公开(公告)号：JP2001085482A
公开(公告)日：2001-03-30
申请号：JP26070099
申请日：1999-09-14
申请人： TOSHIBA CORP
发明人： NODA TOMONOBU , KADOTA KENICHI
IPC分类号： G01N21/956 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To decide accurate defect inspection parameters which are not influenced by the knowledge, etc., of a defect inspection unit, by reducing the occupying time of a defect inspection device. SOLUTION: In this semiconductor inspection method, a pattern image 24 and a defect image 28 by a defect (1) are composed to make a defect inspection image 29 (ST103). Next, the defect of the defect inspection image 29 is inspected simulatively, using a provisional inspection parameter a (STEP105). As a result, defect detection percentage is computed (ST106). In the case that this defect detection percentage fulfills the detection percentage condition being set optionally, the provisional inspection parameter (a) used at this time is decided as an inspection parameter A (ST108). Similarly, an inspection parameter B is detected, using the image of a defect (2) (step110 to ST115). This inspection parameter A and the parameter B are compared with each other, and an optimum inspection parameter C is decided (ST116).

6. 发明专利

JPH08172170A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH08172170A
公开(公告)日：1996-07-02
申请号：JP31649194
申请日：1994-12-20
申请人： TOSHIBA CORP
发明人： NODA TOMONOBU , MAEDA TORU
IPC分类号： H01L21/8242 , H01L27/108
摘要： PURPOSE: To reduce cell area by forming the capacitor of a DRAM cell having a trench type capacitor just under a transistor for a transfer gate. CONSTITUTION: A polysilicon film 6 of 300nm in thickness is formed on the whole surface of a substrate, and doped with impurities to form the plate of a capacitor. A silicon nitride film 8 of 5nm in thickness and a silicon oxide film 9 having the same thickness are formed, and an impurity-doped silicon film 10 of 300nm in thickness which turns to a storage node is formed. Thus a capacitor is formed. A gate insulating film 17 and a gate wiring 11 are formed on a silicon single crystal film 15, and the source region 12a and the drain region 12b of a transistor for a transfer gate are formed on the surface layer part of the silicon single crystal film 15. Hence the transistor for a transfer gate is completed. Thus the cell area is reduced by forming the capacitor of a DRAM cell just under the transistor for a transfer gate.

7. 发明专利

JPH07273218A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH07273218A
公开(公告)日：1995-10-20
申请号：JP6185894
申请日：1994-03-31
申请人： TOSHIBA CORP
发明人： NODA TOMONOBU , NISHIKAWA KENICHI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To make up for the resolution limitation of a lithography technique so as to carry out a finer processing by a method wherein a second etching mask material is formed on the side wall of a groove provided to a first etching mask material which is set as wide as prescribed, and a third etching mask material is formed inside the groove and flattened by polishing. CONSTITUTION:A silicon oxide film 12 is formed through an LPCVD on the surface of a semiconductor substrate 11 where an element isolating region 15 is formed through a selective oxidation method, a silicon nitride film 13 is provided on the film 12, and a silicon oxide film 14 is formed on the film 13. A photoresist film is formed on the surface of the silicon oxide film 14 and patterned as large in width as prescribed or a first width W1, the silicon oxide films 12 and 14 and the silicon nitride film 13 are anisotropically etched, and the semiconductor substrate 1 is exposed as wide as W1. In succession, etching is performed so as to leave the silicon nitride film only on the side face of a mask material for the formation of a second mask, and furthermore a third mask is formed the same as above. This mask is polished, photoresist is applied, and then etching is carried out.

8. 发明专利

JP2001337047A SIMULATED DEFECT WAFER AND METHOD FOR FORMING DEFECT INSPECTION RECIPE 失效
公开(公告)号：JP2001337047A
公开(公告)日：2001-12-07
申请号：JP2000160506
申请日：2000-05-30
申请人： TOSHIBA CORP
发明人： NODA TOMONOBU
IPC分类号： G01B21/30 , G01N21/956 , H01L21/66 , H01L23/544
摘要： PROBLEM TO BE SOLVED: To provide a method for forming independently of a proficiency of a former an optimum defect inspection recipe whereby all kinds of defects can be detected. SOLUTION: A temporary inspection recipe is formed with the use of the simulated defect wafer 1 including simulated defect patterns DF1-DF3 having a change in a height direction and a change in a plane shape to a simulation normal pattern. Defect inspection of the simulated defect wafer 1 is carried out. Detected defect data are compared with preliminarily obtained simulated defect data of the simulated defect wafer 1 to quantify a defect detection sensitivity. Recipe parameters are changed until a desired defect detection rate is obtained. The temporary inspection recipe is thus formed.

9. 发明专利

JP2002299396A METHOD FOR EVALUATING FABRICATION PROCESS OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002299396A
公开(公告)日：2002-10-11
申请号：JP2001095968
申请日：2001-03-29
申请人： TOSHIBA CORP
发明人： NODA TOMONOBU
IPC分类号： G01B21/00 , G06F17/50 , G06T1/00 , G06T7/00 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To provide a method for evaluating the fabrication process of a semiconductor device in which interlayer shift can be evaluated without forming all layers to be evaluated. SOLUTION: The method for evaluating the fabrication process of a semiconductor device comprises a step (ST5) for acquiring a wiring pattern image from a sample where the image of wiring pattern of some layer in the semiconductor device can be picked up, a step (ST8) for synthesizing the wiring pattern in the wiring pattern image and a plurality of CAD data including that of a wiring layer from which the wiring pattern image is acquired to form synthesis data, and a step (ST10) for determining the overlap of the wiring pattern image and the CAD data of a layer other than the wiring pattern layer in the evaluation data wherein the positional coordinate of the wiring pattern in the wiring pattern image is matched to the positional coordinate of the CAD data of the wiring layer.

10. 发明专利

JP2002093875A METHOD OF EVALUATING HAZARDOUS SPOT INFORMATION ON PATTERN OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002093875A
公开(公告)日：2002-03-29
申请号：JP2000277125
申请日：2000-09-12
申请人： TOSHIBA CORP
发明人： NODA TOMONOBU , AKIYAMA TATSUO
IPC分类号： G01B21/20 , G01N23/225 , H01L21/66 , H01L23/58
摘要： PROBLEM TO BE SOLVED: To provide information that is effective for specifying or analyzing, such a hazardous spot as the thinned-off spot, etc., which is difficult to be specified visually in a pattern. SOLUTION: With respect to hazardous spot information on the pattern of a semiconductor device, the difference between first pattern data corresponding to a case, where no dangerous spot exists in the pattern and second pattern data corresponding to another case, where a dangerous spot exists in the pattern is visually displayed as feature data indicating the feature of the hazardous spot. At displaying of a spot causing pattern misregistration as a dangerous spot, the magnitude and the direction of the misregistration are displayed as the direction of a mark.

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