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1. 发明专利

JP2014158012A Pattern inspection method and manufacturing management system 审中-公开
标题翻译：模式检验方法与制造管理系统
公开(公告)号：JP2014158012A
公开(公告)日：2014-08-28
申请号：JP2013180368
申请日：2013-08-30
申请人： Toshiba Corp , 株式会社東芝
发明人： KAWABATA KENJI , KOIKE TORU , KADOTA KENICHI
IPC分类号： H01L21/02 , H01L21/3065
CPC分类号： G01N23/2251 , G01B2210/56 , H01L22/12
摘要： PROBLEM TO BE SOLVED: To provide a pattern inspection method capable of a low-cost and high-speed pattern inspection and a manufacturing management system capable of manufacturing a semiconductor device at low cost and with high throughput.SOLUTION: A pattern inspection method of an embodiment includes the steps of: performing the modeling of the shape simulation of a pattern; measuring, in line, management parameters to be managed in a pattern manufacturing step; executing the shape simulation by using a result of the in-line measurement; and determining pass or fail of the pattern shape on the basis of a result of the shape simulation.
摘要翻译：要解决的问题：提供一种能够以低成本和高产量制造半导体器件的能够进行低成本和高速模式检查的模式检查方法以及制造管理系统。解决方案：实施例包括以下步骤：对图案的形状模拟进行建模; 测量在图案制造步骤中管理的管理参数; 通过使用在线测量的结果来执行形状模拟; 并且基于形状模拟的结果来确定图案形状的通过或失败。

2. 发明专利

JP2010103389A Method of manufacturing semiconductor memory 审中-公开
标题翻译：制造半导体存储器的方法
公开(公告)号：JP2010103389A
公开(公告)日：2010-05-06
申请号：JP2008275130
申请日：2008-10-27
申请人： Toshiba Corp , 株式会社東芝
发明人： IGUCHI SUNAO , BABA MASANOBU , TAKAHATA KAZUHIRO , NAKAJIMA FUMIHARU , MUKAI HIDEFUMI , EMA TATSUHIKO , KAWAI BURANDO , KADOTA KENICHI , KIKUTANI KEISUKE
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor memory high in accuracy of widths of line and space.
SOLUTION: The method of manufacturing the semiconductor memory includes steps of: forming a first pattern constituted of a silicon material film on a film to be worked; oxidizing both side surfaces and an upper surface of the first pattern to form a silicon oxide film and removing a part of the silicon oxide film formed on the upper surface to form a second pattern constituted of the silicon oxide films formed on both side surfaces; removing the first pattern to form a mask pattern constituted of the second pattern; and working the film to be worked, exposed from the mask pattern.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种高线性和空间宽度精度的半导体存储器的制造方法。解决方案：制造半导体存储器的方法包括以下步骤：在待加工的膜上形成由硅材料膜构成的第一图案; 氧化第一图案的两个侧表面和上表面以形成氧化硅膜并去除形成在上表面上的氧化硅膜的一部分，以形成由形成在两个侧表面上的氧化硅膜构成的第二图案; 去除第一图案以形成由第二图案构成的掩模图案; 并将电影工作，从面具图案中露出。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2009206439A Linear pattern detection method and apparatus 有权
标题翻译：线性图案检测方法和装置
公开(公告)号：JP2009206439A
公开(公告)日：2009-09-10
申请号：JP2008049901
申请日：2008-02-29
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUSHITA HIROSHI , KADOTA KENICHI , ARITAKE TOSHIYUKI
IPC分类号： H01L21/66
CPC分类号： G06K9/4604 , G06T7/0004 , G06T2207/20021 , G06T2207/30148
摘要： PROBLEM TO BE SOLVED: To provide a linear pattern detection method capable of extracting and detecting, without being affected by thinning-out measurement, a linear pattern characterized in a shape in which microscopic defects are dispersed.
SOLUTION: The linear pattern detection method includes the steps of: obtaining a defect inspection map created based on the result of a wafer defect inspection; dividing the defect inspection map into a plurality of segments; calculating a correlation coefficient by regarding a defect group included in each of the divided segment as a dot sequence; determining that the segment has a linear defect, if the calculated correlation coefficient exceeds a first threshold value; and determining that the wafer has a first type of linear pattern, if a total number of the segments determined to have the linear defect exceeds a second threshold value.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种线性图案检测方法，其能够提取和检测不受稀释测量的影响，其特征在于分散有微观缺陷的形状的线性图案。线性模式检测方法包括以下步骤：获得基于晶片缺陷检查的结果创建的缺陷检查图; 将缺陷检查图划分为多个段; 通过将包含在每个分割段中的缺陷组视为点序列来计算相关系数; 如果所计算的相关系数超过第一阈值，则确定所述段具有线性缺陷; 以及如果确定为具有所述线性缺陷的段的总数超过第二阈值，则确定所述晶片具有第一类型的线性模式。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2012175080A Defect inspection method and defect inspection device 审中-公开
标题翻译：缺陷检查方法和缺陷检查装置
公开(公告)号：JP2012175080A
公开(公告)日：2012-09-10
申请号：JP2011038844
申请日：2011-02-24
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKA MASATO , YAMAGUCHI SHINJI , MITSUI TADASHI , KADOTA KENICHI , ABE HIDEAKI
IPC分类号： H01L21/66 , G01N21/956
摘要： PROBLEM TO BE SOLVED: To provide a method of removing a defect which does not greatly influence the yield of semiconductor devices and reduces the manufacturing costs needed to cope therewith.SOLUTION: The method includes a step ST11A of inspecting whether a first inspection object includes a defect; a step ST11B of classifying detected defects by features and calculating the numbers of defects by features of the defects; steps ST12B and ST12C of measuring electric characteristics of semiconductor devices on a wafer and creating a defect map of the semiconductor devices on the wafer; steps ST13 and ST14 of collating the defect map with the position of the defect of the inspection object and calculating an electric defect probability of the semiconductor devices; and a step STn of determining whether a second inspection object can be used using the electric defect probability.
摘要翻译：要解决的问题：提供一种去除不会极大影响半导体器件的产量的缺陷的方法，并降低了处理所需的制造成本。解决方案：该方法包括检查第一检查对象是否包括缺陷的步骤ST11A; 通过特征分类检测到的缺陷并通过缺陷的特征来计算缺陷数的步骤ST11B; 步骤ST12B和ST12C，测量晶片上的半导体器件的电特性并产生半导体器件在晶片上的缺陷图; 将缺陷图与检查对象的缺陷的位置对准并计算半导体器件的电缺陷概率的步骤ST13和ST14; 以及使用电缺陷概率来确定是否能够使用第二检查对象的步骤STn。版权所有（C）2012，JPO＆INPIT

5. 发明专利

JP2007116182A Defect detection method 有权
标题翻译：缺陷检测方法
公开(公告)号：JP2007116182A
公开(公告)日：2007-05-10
申请号：JP2006306748
申请日：2006-11-13
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUSHITA HIROSHI , KADOTA KENICHI
IPC分类号： H01L21/66 , G01R31/26
摘要： PROBLEM TO BE SOLVED: To provide a defect detection method capable of detecting any faulty manufacturing equipment used in a manufacturing process for a semiconductor integrated circuit in accordance with a distribution of defects which have occurred on each wafer basis. SOLUTION: The defect detection method includes the steps for: setting many regional segments for a wafer; extracting the defect position information on a target wafer within a lot to be tested; calculating a first wafer feature amount for which any deviation in a distribution of defects occurred within a wafer surface on each target wafer basis is quantified in accordance with the regional segments; calculating the first wafer feature amount on each target wafer basis from the resultant first wafer feature amount; extracting the manufacturing equipment used in a manufacturing process on each target lot basis from the process history information; verifying the significant difference among the manufacturing equipment used in each manufacturing process on each first lot feature amount basis; and detecting the manufacturing equipment with any significant difference as a first faulty equipment. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够根据每个晶片基础上发生的缺陷的分布来检测在半导体集成电路的制造工艺中使用的任何故障制造设备的缺陷检测方法。解决方案：缺陷检测方法包括以下步骤：为晶片设置许多区域段; 在待测试的批次内的目标晶片上提取缺陷位置信息; 计算在每个目标晶片基础上在晶片表面内发生的缺陷分布的任何偏差的第一晶片特征量根据区域段进行量化; 从所得第一晶片特征量计算每个目标晶片基础上的第一晶片特征量; 从过程历史信息中提取在每个目标批次上的制造过程中使用的制造设备; 验证每个制造过程中使用的制造设备在每个第一批次特征量基础上的显着差异; 并且检测与第一故障设备有任何显着差异的制造设备。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2005032925A Abnormality detection system of manufacturing apparatus, method of detecting abnormality of the apparatus, and abnormality detection program of the apparatus 有权
标题翻译：制造装置的异常检测系统，检测装置异常的方法和装置的异常检测程序
公开(公告)号：JP2005032925A
公开(公告)日：2005-02-03
申请号：JP2003195124
申请日：2003-07-10
申请人： Toshiba Corp , 株式会社東芝
发明人： KADOTA KENICHI
IPC分类号： H01L21/02 , G06F11/30
CPC分类号： G06F11/008
摘要： PROBLEM TO BE SOLVED: To provide an abnormality detection system of a manufacturing apparatus, a method of detecting abnormalities in the apparatus and an abnormality detection program for the apparatus, with which detection sensitivity can be improved and misinformation can be reduced.
SOLUTION: The method of detecting abnormalities in the manufacturing apparatus includes steps of extracting an apparatus holding a period of a significantly lower yield than other manufacturing apparatuses and a significant low yield period, by comparing yields of a plurality of manufacturing apparatuses concurrently used in a specific manufacturing process for each of the periods of their use; extracting an apparatus with a degrading trend with the yield significantly decreasing compared with the other apparatuses, by comparing recent yield trends of the plurality of apparatuses; and issuing an alarm stepped in a plurality of levels to the apparatus holding the low yield period and the apparatus with the degrading trend.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种制造装置的异常检测系统，检测装置中的异常的方法和用于该装置的异常检测程序，能够提高检测灵敏度并且可以降低误信息。解决方案：在制造装置中检测异常的方法包括以下步骤：通过比较同时使用的多个制造装置的产量，提取保持比其他制造装置低得多的时间段和显着的低产量周期的装置在其使用的每个周期的具体制造过程中; 通过比较多个装置的近期产量趋势，提取具有降级趋势的装置，其产量与其他装置相比显着降低; 并且向保持低收益期的装置发出多层次的报警和具有降级趋势的装置。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2003037143A System, method and program for analyzing cause of fault, method for manufacturing industrial product 审中-公开
标题翻译：用于分析故障原因的系统，方法和程序，制造工业产品的方法
公开(公告)号：JP2003037143A
公开(公告)日：2003-02-07
申请号：JP2001222925
申请日：2001-07-24
申请人： Toshiba Corp , 株式会社東芝
发明人： KADOTA KENICHI
IPC分类号： H01L21/66 , H01L21/02
摘要： PROBLEM TO BE SOLVED: To detect a systematic fault caused by a manufacturing process and identify the process as the cause of the fault.
SOLUTION: A system for analyzing the cause of the fault includes a testing apparatus 20, a yield memory 14, a test result memory 15 and a process controller (CPU) 100. The CPU 100 includes a yield analyzing means 16, a means for analyzing an occurring location on a surface 17, a means for analyzing correlation on the surface 18 and a means for displaying an analyzed result 19. The yield analyzing means 16 calculates the yield based on a result from the testing apparatus 20. The means for analyzing the occurring location on the surface 17 identifies a systematic fault area 5 on the surface of a wafer based on the result from the testing apparatus 20 and the yield calculated by the yield analyzing means 16. The means for analyzing the correlation on the surface 18 identifies the cause of the fault based on the systematic faulty area 5 and a process managing data 6.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：检测由制造过程引起的系统故障，并将过程识别为故障的原因。解决方案：用于分析故障原因的系统包括测试装置20，产量存储器14，测试结果存储器15和过程控制器（CPU）100.CPU 100包括产量分析装置16，用于分析的装置表面17上的发生位置，用于分析表面18上的相关性的装置和用于显示分析结果的装置19.成品率分析装置16基于来自测试装置20的结果来计算产量。表面17上的发生位置基于来自测试装置20的结果和由成品率分析装置16计算的收益来识别晶片表面上的系统故障区域5.用于分析表面18上的相关性的装置识别出基于系统故障区5的故障原因和管理数据6的过程。

8. 发明专利

JP2005092466A Diagnostic process supporting method and its program 审中-公开
标题翻译：诊断过程支持方法及其程序
公开(公告)号：JP2005092466A
公开(公告)日：2005-04-07
申请号：JP2003323778
申请日：2003-09-16
申请人： Toshiba Corp , 株式会社東芝
发明人： OZAWA MASANORI , KADOTA KENICHI , MATSUSHITA HIROSHI , KUROIWA TADASHI
IPC分类号： G05B11/32 , G05B13/02 , G05B23/02
摘要： PROBLEM TO BE SOLVED: To provide a method and program for supporting an operator to easily and efficiently perform an operation to decide the optimal conditions including the combination of the "adoption number of variables(featured values)" and "thresholds" for optimizing decision precision. SOLUTION: After the learning of a unit space (401) and the Mahalanobis distance calculation of data to be analyzed (S402), the valid sequence of those variables is decided (S403). In two-dimensional plot processing (S410), two variables are adopted in the order of validity (S411), and thresholds are gradually increased from a small size to a large size, and the distribution of erroneously decision rates is calculated (S412). Then, the erroneous decision rates are plotted on the picture of a two-dimensional graph whose one axis shows thresholds and whose other axis shows the adoption number of variables(featured values) (S413). A series of operations to gradually increase the thresholds, and to calculate the distribution of the erroneous rates (S412), and to plot the erroneous rates (S413) are repeated while the adoption number of variables is increased one by one (S415) so that a two-dimensional figure can be plotted. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种方法和程序，用于支持操作者容易且有效地执行操作以决定包括“变量的采用数（特征值）”和“阈值”的组合的最佳条件优化决策精度。解决方案：在学习单位空间（401）和要分析的数据的马哈拉诺比斯距离计算（S402）之后，确定这些变量的有效序列（S403）。在二维绘图处理（S410）中，以有效性顺序采用两个变量（S411），阈值从小尺寸逐渐增加到大尺寸，并计算错误判定率的分布（S412）。然后，错误的判定率绘制在二维图的图中，其一轴显示阈值，其另一轴表示变量的采用数（特征值）（S413）。重复逐步增加阈值的一系列操作，并计算错误率的分布（S412），并绘制错误率（S413），同时逐个增加变量的采用数（S415），以便可以绘制二维图。版权所有（C）2005，JPO＆NCIPI

9. 发明专利

JP2004288743A Device, method, and program for failure analysis 有权
公开(公告)号：JP2004288743A
公开(公告)日：2004-10-14
申请号：JP2003076411
申请日：2003-03-19
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUSHITA HIROSHI , KAWABATA KENJI , KADOTA KENICHI , SHIOYAMA YOSHIYUKI
IPC分类号： H01L21/66 , H03K19/003
CPC分类号： H01L22/20
摘要： PROBLEM TO BE SOLVED: To provide a failure analysis method capable of automatically sorting out the distribution of failures that occur in each wafer by the wafer. SOLUTION: The occurrence positions of failures occurring in a plurality of wafers are inputted. The wafer is partitioned into a plurality of regions. A computation is carried out so as to represent the amount of features of a failure distribution in each region of the wafer by, at least, one or more kinds of numerical values. As to the amount of features, the degree of similarity among the wafers is represented by a first numerical value. For each wafer, other wafers having the first numerical values above a predetermined first threshold value are extracted, and similar wafer groups composed of wafers which are similar to each other in a failure distribution are formed. COPYRIGHT: (C)2005,JPO&NCIPI

10. 发明专利

JP2001085482A DEVICE AND METHOD FOR SEMICONDUCTOR INSPECTION 失效
公开(公告)号：JP2001085482A
公开(公告)日：2001-03-30
申请号：JP26070099
申请日：1999-09-14
申请人： TOSHIBA CORP
发明人： NODA TOMONOBU , KADOTA KENICHI
IPC分类号： G01N21/956 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To decide accurate defect inspection parameters which are not influenced by the knowledge, etc., of a defect inspection unit, by reducing the occupying time of a defect inspection device. SOLUTION: In this semiconductor inspection method, a pattern image 24 and a defect image 28 by a defect (1) are composed to make a defect inspection image 29 (ST103). Next, the defect of the defect inspection image 29 is inspected simulatively, using a provisional inspection parameter a (STEP105). As a result, defect detection percentage is computed (ST106). In the case that this defect detection percentage fulfills the detection percentage condition being set optionally, the provisional inspection parameter (a) used at this time is decided as an inspection parameter A (ST108). Similarly, an inspection parameter B is detected, using the image of a defect (2) (step110 to ST115). This inspection parameter A and the parameter B are compared with each other, and an optimum inspection parameter C is decided (ST116).

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