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    • 1. 发明专利
    • 高周波特性測定治具装置
    • 高频特性测量装置
    • JP2015052574A
    • 2015-03-19
    • JP2013186735
    • 2013-09-09
    • 株式会社東芝Toshiba Corp
    • NG CHOON YONG
    • G01R31/26
    • G01R31/2601G01R1/045H01L22/14
    • 【課題】精度良く高周波素子を測定可能な高周波特性測定治具装置を提供する。【解決手段】接地導体部10と、第1のコプレーナ線路20と、接続基板30と、押さえ部と、を有する。第1のコプレーナ線路20は、第1の誘電体層21と、第1の中心導電層22と、第1の接地導電層26と、を有する。接続基板30は、第2の誘電体層31と、第2の中心導電層32と、第2の接地導電層36と、第3の接地導電層40と、を有する。第2の誘電体層31は、第2の導電層32と第2の接地導電層36とが設けられる第1領域LAと、第2の接地導電層36が設けられない第2領域RAと、を有する。押さえ部は、第1と第2の中心導電層22、32の間、第1と第2の接地導電層26、36の間、第2領域RAの第2の中心導電層32と信号端子50aとを導通可能とするように、接続基板30を第1のコプレーナ線路20と信号端子50aとにそれぞれ押圧する。【選択図】図3
    • 要解决的问题:提供能够精确测量高频元件的高频特性测量夹具装置。解决方案:一种高频特性测量夹具装置,包括:接地导体部分10; 第一共面线20; 连接基板30; 和按压部。 第一共面线20包括第一介电层21,第一中心导电层22和第一接地导电层26.连接基板30包括第二电介质层31,第二中心导电层32,第二接地导电层 36和第三接地导电层40.第二介电层31包括:设置有第二导电层32和第二接地导电层36的第一区域LA; 以及不设置第二接地导电层36的第二区域RA。 按压部分将连接基板30压在第一共面线20和信号端子50a中的每一个上,以在第一和第二接地导电层26和36之间实现第一和第二中心导电层22和32之间的导电 并且在第二区域RA中的第二中心导电层32和信号端子50a之间。
    • 2. 发明专利
    • Semiconductor power amplifier
    • 半导体功率放大器
    • JP2013004786A
    • 2013-01-07
    • JP2011135157
    • 2011-06-17
    • Toshiba Corp株式会社東芝
    • NG CHOON YONG
    • H01L21/8232H01L21/3205H01L21/768H01L21/82H01L21/822H01L23/522H01L27/04H01L27/06H01L27/095H03F3/19H03F3/20H03F3/60
    • H01L29/4175H01L23/481H01L23/4824H01L23/5227H01L23/645H01L28/10H01L29/41758H01L2924/0002H01L2924/00
    • PROBLEM TO BE SOLVED: To provide a semiconductor power amplifier in which a characteristic degradation such as loop oscillation is hard to occur even if the number of via holes is decreased.SOLUTION: The semiconductor power amplifier includes a unit FET containing a gate electrode G, a drain electrode D, and two source electrodes S drawn out to both sides in lateral direction of a source finger electrode arranged to face a gate finger electrode. The unit FET includes a first via hole 18K having a first grounding inductance value which is arranged parallel to each other by a plurality of numbers in the direction of almost straight line connecting the source electrodes together, for connecting both the two source electrodes present between adjoining unit FETs to a high frequency ground surface in common, and a second via hole 18D having a second grounding inductance value which is arranged on the source electrode that is on the side where adjoining unit FETs are not present, for connecting to the high frequency ground surface so as to provide an equal ground inductance.
    • 要解决的问题:即使通孔的数量减少,也提供其中难以发生诸如环路振荡之类的特性劣化的半导体功率放大器。 解决方案:半导体功率放大器包括单元FET,其包含栅极电极G,漏极电极D和两个源极电极S,该栅极电极设置为与栅极指状电极相对配置的源极指状电极的横向方向两侧。 单元FET包括第一通孔18K,第一通孔18K具有第一接地电感值,该第一接地电感值在将源电极连接在一起的几乎直线的方向上以多个数字彼此平行布置,用于连接存在于相邻的两个源极之间的两个源电极 单元FET共同连接到高频地表面,以及第二通孔18D,其具有布置在源电极上的第二接地电感值,所述第二接地电感值位于相邻单元FET不存在的一侧,用于连接到高频地 以提供相等的接地电感。 版权所有(C)2013,JPO&INPIT
    • 4. 发明专利
    • Semiconductor device having stabilization circuit
    • 具有稳定电路的半导体器件
    • JP2013070403A
    • 2013-04-18
    • JP2012248201
    • 2012-11-12
    • Toshiba Corp株式会社東芝
    • NG CHOON YONGTAKAGI KAZUTAKATOMITA NAOTAKA
    • H03F3/20H01L21/338H01L21/822H01L27/04H01L27/095H01L29/778H01L29/812H01L47/02H03B7/08H03F1/08
    • PROBLEM TO BE SOLVED: To provide a semiconductor device having a stabilization circuit capable of obtaining stable and high-efficient power amplification by preventing negative resistance associated with a Gunn oscillation.SOLUTION: A semiconductor device includes: a substrate 10; an active element 140 that is disposed on the substrate and generates negative resistance at an oscillation frequency of a high-frequency negative resistance oscillation that is a Gunn oscillation; and a stabilization circuit 120 that is disposed on the substrate and is composed of a resistor R that is connected between a drain terminal electrode and an output terminal of the active element and has a resistance value equivalent to the absolute value of the negative resistance, and a tank circuit that is connected in parallel to the resistor R and is composed of an inductor L and a capacitor C that are tunable to the oscillation frequency of high-frequency negative resistance oscillation. The stabilization circuit 120 cancels the negative resistance by the resistor R at the oscillation frequency by tuning the oscillation frequency to the resonant frequency composed of the inductor L and the capacitor C.
    • 要解决的问题:提供一种具有稳定电路的半导体器件,该稳定电路能够通过防止与耿氏振荡相关的负电阻而获得稳定和高效的功率放大。 解决方案:半导体器件包括:衬底10; 设置在基板上的有源元件140,以高频负电阻振荡的振荡频率产生作为耿氏振荡的负电阻; 以及稳定电路120,其设置在基板上,由连接在有源元件的漏极端子电极和输出端子之间的电阻器R构成,具有与负电阻的绝对值相当的电阻值,以及 与电阻器R并联连接并由可调谐到高频负电阻振荡的振荡频率的电感器L和电容器C构成的振荡电路。 稳定电路120通过将振荡频率调谐到由电感器L和电容器C组成的谐振频率,以振荡频率抵消电阻器R的负电阻。(C)2013,JPO&INPIT
    • 6. 发明专利
    • Package device
    • 包装设备
    • JP2013118571A
    • 2013-06-13
    • JP2011265789
    • 2011-12-05
    • Toshiba Corp株式会社東芝
    • NG CHOON YONG
    • H01P3/08
    • PROBLEM TO BE SOLVED: To provide a package device which shortens a path length of a ground current between substrates and achieves excellent high frequency performance.SOLUTION: A package device according to one embodiment comprises: a first ground conductor layer where a first ground pattern is formed; a first substrate disposed on an upper surface of the first ground conductor layer and where a first line pattern is formed; a second ground conductor layer disposed on the upper surface of the first ground conductor layer and where a second ground pattern is formed; a second substrate disposed on an upper surface of the second ground conductor layer and where a second line pattern is formed; and a first bonding wire connecting the first line pattern with the second line pattern. An inclination is formed at a connection part on the upper surface of the first ground conductor layer, the connection part connecting with the second ground conductor layer. An inclination is formed at a connection part on a bottom surface of the second ground conductor layer, the connection part connecting with the first ground conductor layer, so as to fit in the inclination of the connection part on the upper surface of the first ground conductor layer.
    • 要解决的问题:提供一种缩短基板之间的接地电流的路径长度并且实现优异的高频性能的封装装置。 解决方案:根据一个实施例的封装器件包括:形成第一接地图案​​的第一接地导体层; 设置在所述第一接地导体层的上表面上并且形成第一线图案的第一基板; 设置在第一接地导体层的上表面上并形成第二接地图案的第二接地导体层; 设置在所述第二接地导体层的上表面上并且形成第二线图案的第二基板; 以及将第一线图案与第二线图案连接的第一接合线。 在第一接地导体层的上表面上的连接部分形成倾斜,连接部分与第二接地导体层连接。 在第二接地导体层的底表面上的连接部分形成倾斜,连接部分与第一接地导体层连接,以便配合在第一接地导体的上表面上的连接部分的倾斜度 层。 版权所有(C)2013,JPO&INPIT
    • 8. 发明专利
    • Semiconductor device
    • 半导体器件
    • JP2011029966A
    • 2011-02-10
    • JP2009174003
    • 2009-07-27
    • Toshiba CorpToshiba Denpa Components Kk東芝電波コンポーネンツ株式会社株式会社東芝
    • NG CHOON YONGTAKAGI KAZUTAKATOMITA NAOTAKA
    • H03F3/213H01L21/822H01L27/04
    • H03F1/086H03F1/14H03F3/193H03F3/211
    • PROBLEM TO BE SOLVED: To provide a semiconductor device provided with a stabilization circuit for suppressing odd-mode oscillations, suppressing negative resistance with gun oscillation and obtaining stable and high-efficiency power amplification. SOLUTION: The semiconductor device includes a first active element FET1, a second active element FET2 connected in parallel with the first active element FET1, and a first stabilization circuit 120, which is connected between a gate G1 of the first active element FET1 and a gate G2 of the second active element FET2 and consists of a parallel circuit of a gate bypass resistor Rg 0 , a gate bypass capacitor Cg 0 and a gate bypass inductor Lg 0 , wherein the first stabilization circuit 120 has a resonant frequency equal to an odd-mode resonant frequency. COPYRIGHT: (C)2011,JPO&INPIT
    • 要解决的问题:提供一种具有用于抑制奇数振荡的稳定电路的半导体器件,用枪振荡抑制负电阻并获得稳定和高效的功率放大。 解决方案:半导体器件包括与第一有源元件FET1并联连接的第一有源元件FET1,第二有源元件FET2和连接在第一有源元件FET1的栅极G1之间的第一稳定电路120 和第二有源元件FET2的栅极G2,由栅极旁路电阻器Rg 0 和栅极旁路电容器Cg 0 和栅极旁路电感器Lg 其中第一稳定电路120具有等于奇数共振频率的谐振频率。 版权所有(C)2011,JPO&INPIT