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1. 发明专利

JP2014170789A Semiconductor device, and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2014170789A
公开(公告)日：2014-09-18
申请号：JP2013040655
申请日：2013-03-01
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO YOSHINOBU , KATO ATSUSHI , OMOTO SEIICHI , NAKAJIMA KAZUAKI , TOYODA HIROSHI
IPC分类号： H01L27/115 , H01L21/3065 , H01L21/3205 , H01L21/336 , H01L21/768 , H01L21/8247 , H01L27/10 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To thin a wiring pattern while reducing the number of steps in a side wall processing process.SOLUTION: A side wall pattern 6A consisting of a conductor is formed on a side wall of a core material pattern 3A. The core material pattern 3A is removed while remaining the side wall pattern 6A on a seed layer 2. The seed layer 2 is etched via the side wall pattern 6A. Thereby, a wire consisting of the side wall pattern 6A and the seed layer 2 is formed on a base layer 1.
摘要翻译：要解决的问题：减少侧壁加工工艺中的步骤数量，减少布线图案。解决方案：在芯材图案3A的侧壁上形成由导体构成的侧壁图案6A。芯材料图案3A被去除，同时保留在种子层2上的侧壁图案6A。籽晶层2经由侧壁图案6A被蚀刻。由此，在基底层1上形成由侧壁图案6A和种子层2构成的线。

2. 发明专利

JP2013172103A Method of forming interconnection 审中-公开
标题翻译：形成互连的方法
公开(公告)号：JP2013172103A
公开(公告)日：2013-09-02
申请号：JP2012036733
申请日：2012-02-22
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO KAZUMASA , TOYODA HIROSHI , ITO YOSHINOBU , OMOTO SEIICHI , MORITA TOSHIYUKI , YAMAZAKI SOICHI
IPC分类号： H01L21/768 , H01L21/306 , H01L21/3065 , H01L21/3205 , H01L23/532
摘要： PROBLEM TO BE SOLVED: To provide a method of forming an interconnection which allows for excellent filling of a groove, for forming an interconnection of narrow pattern, with a wiring material when forming an interconnection mixing a wide wiring pattern and a narrow wiring pattern by damascene method.SOLUTION: At first, a wiring groove 11a of first width and a wiring groove 11b of second width are formed in an interlayer insulation film 11. A barrier metal film 12 is then formed on the interlayer insulation film 11, and a W film 13 is formed with a thickness for filling the wiring groove 11a but not filling the wiring groove 11b. Subsequently, the barrier metal film 12 and the W film 13 on the interlayer insulation film 11 are removed by etching. Thereafter, a barrier metal film 14 is formed on the entire surface of the interlayer insulation film 11, and a Cu film 15 is formed on the barrier metal film 14 so as to fill the wiring groove 11b. Finally, the barrier metal film 14 and the Cu film 15 on the interlayer insulation film 11 are removed.
摘要翻译：要解决的问题：提供一种形成互连的方法，其能够在通过镶嵌形成互连混合宽布线图案和窄布线图案的布线时，与用布线材料形成沟槽的优良填充，用于形成窄图案的互连方法。首先，在层间绝缘膜11中形成第一宽度的布线槽11a和第二宽度的布线槽11b。然后在层间绝缘膜11上形成阻挡金属膜12，并且将W膜 13形成有用于填充布线槽11a但不填充布线槽11b的厚度。随后，通过蚀刻去除层间绝缘膜11上的阻挡金属膜12和W膜13。此后，在层间绝缘膜11的整个表面上形成阻挡金属膜14，并且在阻挡金属膜14上形成Cu膜15以填充布线槽11b。最后，去除层间绝缘膜11上的阻挡金属膜14和Cu膜15。

3. 发明专利

JP2013026241A Deposition apparatus and deposition method 审中-公开
标题翻译：沉积装置和沉积方法
公开(公告)号：JP2013026241A
公开(公告)日：2013-02-04
申请号：JP2011156162
申请日：2011-07-14
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO YOSHINOBU
IPC分类号： H01L21/285 , C23C16/04 , C23C16/14 , H01L21/3205 , H01L21/768 , H01L23/532
摘要： PROBLEM TO BE SOLVED: To provide a deposition apparatus and a deposition method which prevent a semiconductor wafer from being etched when depositing a tungsten film.SOLUTION: The deposition apparatus comprises a stage on which a semiconductor wafer is mounted, and an edge cut placed to cover the peripheral edge of the semiconductor wafer being mounted on the stage, and a tungsten film is deposited on the semiconductor wafer. The edge cut includes a first edge cut provided so as to come into contact with the peripheral edge of the semiconductor wafer, a connection connected with the first edge cut and movable vertically in a direction substantially perpendicular to the semiconductor wafer, and a second edge cut connected with the connection and placed to abut against the inner side surface of the semiconductor wafer by vertical motion of the connection.
摘要翻译：要解决的问题：提供一种当沉积钨膜时防止半导体晶片被蚀刻的沉积设备和沉积方法。解决方案：沉积设备包括其上安装有半导体晶片的台，以及覆盖安装在台架上的半导体晶片的周边边缘的边缘切割，并且在半导体晶片上沉积钨膜。边缘切割包括设置成与半导体晶片的周缘接触的第一边缘切割，与第一边缘切割并且在基本上垂直于半导体晶片的方向上垂直移动的连接，以及第二边缘切割与连接件连接并且通过连接的垂直运动放置成抵靠半导体晶片的内侧表面。版权所有（C）2013，JPO＆INPIT

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