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1. 发明专利

JP2004087877A Field effect semiconductor device and method for manufacturing the same 审中-公开
标题翻译：场效应半导体器件及其制造方法
公开(公告)号：JP2004087877A
公开(公告)日：2004-03-18
申请号：JP2002248079
申请日：2002-08-28
申请人： Fujitsu Ltd , Toshiba Corp , 富士通株式会社 , 株式会社東芝
发明人： SUGIZAKI TARO , AKASAKA YASUSHI , NAKAJIMA KAZUAKI
IPC分类号： H01L29/423 , H01L21/8242 , H01L27/108 , H01L29/49 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a gate electrode having a high melting metal structure of Si/WSi/WN, low in contact resistance and high in thermal stability. SOLUTION: In the manufacturing of this field effect semiconductor device, it is so set that a mathematical expression d WSi ≤(1.25d WN ) 1/2 be satisfied, wherein d WSi [nm] is the thickness of a WSi layer 6 which is a constituent of a gate electrode 4 having a high melting metal structure of Si/WSi/WN and d WN [nm] is the thickness of a WN layer 7 which is another constituent located farther from a gate insulating film 2 than the WSi layer 6 is. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供具有高熔点金属结构的Si / WSi / WN的栅电极，接触电阻低和热稳定性高。解决方案：在该场效应半导体器件的制造中，将数学表达式设定为数学表达式，其中，数学表达式为：SP1 =（1.25d WN ） 1 / 2 ，其中d WSi [nm]是WSi层6的厚度，WSi层6是具有Si / WSi / WN的高熔融金属结构的栅电极4的组成并且d W N [nm]是与WSi层6相比位于比栅极绝缘膜2更远的另一个成分的WN层7的厚度。版权所有（C）2004，JPO

2. 发明专利

JP2005166707A Semiconductor device and manufacturing method therefor 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005166707A
公开(公告)日：2005-06-23
申请号：JP2003399725
申请日：2003-11-28
申请人： Fujitsu Ltd , Toshiba Corp , 富士通株式会社 , 株式会社東芝
发明人： AKASAKA YASUSHI , SUGIZAKI TARO
IPC分类号： H01L21/28 , H01L29/423 , H01L29/49 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which drop of an operation speed can be prevented, and to provide a manufacturing method of the device.
SOLUTION: The method has a process for forming a gate insulating film 12 on a semiconductor substrate 11; a process for forming a semiconductor film 13 including silicon on the gate insulating film; a process for forming a film 14 including first high melting metal and nitrogen on the semiconductor film; a process for heating semiconductor film and the film including the first high melting metal and nitrogen, and forming a film 15 including the first high melting metal, silicon and nitrogen in a boundary region of the semiconductor film and the film including the first high melting metal and nitrogen; a process for removing the film including the first high melting metal and nitrogen, and exposing the film including the first high melting metal, silicon and nitrogen; and a process for forming a metal film including a second high melting metal on the exposed film including the first high melting metal, silicon and nitrogen.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供可以防止操作速度下降的半导体器件，并提供该器件的制造方法。解决方案：该方法具有在半导体衬底11上形成栅极绝缘膜12的工艺; 在栅极绝缘膜上形成包含硅的半导体膜13的工序; 在半导体膜上形成包括第一高熔点金属和氮的膜14的工艺; 用于加热半导体膜的方法和包括第一高熔点金属和氮的膜，并且在半导体膜的边界区域中形成包括第一高熔点金属，硅和氮的膜15，以及包括第一高熔点金属的膜和氮气; 用于除去包括第一高熔点金属和氮的膜的方法，以及使包含第一高熔点金属，硅和氮的膜暴露; 以及在包括第一高熔点金属，硅和氮的暴露膜上形成包括第二高熔点金属的金属膜的工艺。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2008034751A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008034751A
公开(公告)日：2008-02-14
申请号：JP2006208948
申请日：2006-07-31
申请人： Fujitsu Ltd , Renesas Technology Corp , 富士通株式会社 , 株式会社ルネサステクノロジ
发明人： TAMURA YASUYUKI , NAKADA HIROYUKI , AKASAKA YASUSHI
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To materialize a metal gate CMOS semiconductor device which suppresses damages to a semiconductor substrate, a gate insulating film, and first and second electroconductive layers (metal gate electrode materials) in a production process as much as possible, prevents an increase of a gate resistance value and a gate leakage current, and is extremely high reliable. SOLUTION: A second electroconductive layer 8 and a mask layer 6 are dry-etched by use of a resist mask 9 for removing them. When this takes place, the second electroconductive layer 8 is left so as to cover only a portion equivalent onto an nMOS region 2b following a shape of the resist mask 9 and alienate on an element isolation structure 4 from a first electroconductive layer 5. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：为了实现在制造过程中尽可能地抑制对半导体衬底，栅极绝缘膜以及第一和第二导电层（金属栅电极材料）的损伤的金属栅极CMOS半导体器件，防止栅极电阻值和栅极漏电流的增加，并且极高可靠性。解决方案：通过使用用于去除它们的抗蚀剂掩模9对第二导电层8和掩模层6进行干蚀刻。当发生这种情况时，留下第二导电层8，以仅覆盖与抗蚀剂掩模9的形状相邻的nMOS区域2b上的等同部分，并且在元件隔离结构4上与第一导电层5分离。
版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2007335783A Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：JP2007335783A
公开(公告)日：2007-12-27
申请号：JP2006168431
申请日：2006-06-19
申请人： Fujitsu Ltd , 富士通株式会社
发明人： TAMURA YASUYUKI , NAKADA HIROYUKI , AKASAKA YASUSHI
IPC分类号： H01L21/8238 , H01L21/28 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device having high performance and highly-reliable metal gate electrode.
SOLUTION: A metal gate electrode layer 4 is formed on a gate insulation film 3 formed on a semiconductor substrate 1, a mask layer 5 is formed on the metal gate electrode layer 4, the mask layer 5 of a pMOS formation region 2b is removed, the metal gate electrode layer 4 of the pMOS formation region 2b is removed with the mask layer 5a of an nMOS formation region 2a as a mask, and a metal gate electrode layer 6 is formed on the mask layer 5a and on the gate insulation film 3. A photoresist pattern 7 for masking the pMOS formation region 2b is formed, the metal gate electrode layer 6 of the nMOS formation region 2a is removed with the photoresist pattern 7 as a mask, and the mask layer 5a of the nMOS formation region 2a is removed. Thus, during etching for forming the metal gate electrode on the nMOS formation region 2a and on the pMOS formation region 2b, damage to the gate insulation film 3 and the surface of the semiconductor substrate 1 is prevented.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供具有高性能和高可靠性的金属栅电极的半导体器件的制造方法。解决方案：在形成在半导体衬底1上的栅极绝缘膜3上形成金属栅电极层4，在金属栅电极层4，pMOS形成区2b的掩模层5上形成掩模层5 ，用nMOS形成区域2a的掩模层5a作为掩模去除pMOS形成区域2b的金属栅电极层4，并且在掩模层5a和栅极上形成金属栅电极层6 绝缘膜3.形成用于掩蔽pMOS形成区域2b的光致抗蚀剂图案7，用光致抗蚀剂图案7作为掩模去除nMOS形成区域2a的金属栅电极层6，并且将nMOS形成掩模层5a 区域2a被去除。因此，在用于在nMOS形成区域2a和pMOS形成区域2b上形成金属栅电极的蚀刻期间，防止了栅极绝缘膜3和半导体衬底1的表面的损坏。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2004165174A Method of forming multilayered gate structure 审中-公开
公开(公告)号：JP2004165174A
公开(公告)日：2004-06-10
申请号：JP2002234990
申请日：2002-08-12
申请人： Huabang Electronic Co Ltd , Toshiba Corp , 株式会社東芝 , 華邦電子股▲ふん▼有限公司
发明人： CHIN NOKOKU , AKASAKA YASUSHI
IPC分类号： H01L29/423 , H01L29/49 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a multilayered gate structure composed of a gate oxide layer, a doped silicon layer, a silicon germanium layer, a tungsten nitride layer, and a tungsten layer which are laminated in this sequence.
SOLUTION: A polysilicon layer is doped with bromine. The silicon germanium layer is formed through a separation method or an ion implantation method. Bromine is slowly diffused into the silicon germanium layer in a heating process, so that bromine is hardly diffused into the tungsten nitride layer. Therefore, the contact resistance of the gate structure can be kept at a certain level as desired.
COPYRIGHT: (C)2004,JPO

6. 发明专利

JP2006080354A Manufacturing method of misfet 审中-公开
标题翻译： MISFET的制造方法
公开(公告)号：JP2006080354A
公开(公告)日：2006-03-23
申请号：JP2004263783
申请日：2004-09-10
申请人： Toshiba Corp , 株式会社東芝
发明人： AKASAKA YASUSHI , MIYAGAWA KAZUHIRO , SASAKI TAKAOKI
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of an MISFET having high current driving ability and low power consumption in the MISFET provided with a gate electrode of damascene structure.
SOLUTION: Source/drain diffusion layers (14, 15) are formed on the surfaces of a silicon substrate 1, and a silicide layer 17 is formed on the surface thereof. Then, an interface layer 21 is formed on the silicon substrate 1 at the bottom of a gate opening groove 20 partitioned by gate side walls (12, 13) at a temperature ≤550°C, a High-k film 22 is deposited to cover the interface layer 21 and an interlayer insulating film 19 in the gate opening groove 20, and a heat treatment is carried out at a temperature ≤550°C. Then, after a conductor film 23 and a metal film 24 covering the whole surface are formed, unnecessary portion on the interlayer insulating film 19 is polished and removed by CMP method to form the MISFET provided with the metal gate electrode of damascene structure.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种在具有镶嵌结构的栅电极的MISFET中具有高电流驱动能力和低功耗的MISFET的制造方法。解决方案：在硅衬底1的表面上形成源极/漏极扩散层（14,15），并且在其表面上形成硅化物层17。然后，在栅极开口槽20的底部，在硅衬底1上形成界面层21，栅极开口槽20在温度≤550℃下被栅极侧壁（12,13）分隔，高K膜22沉积到覆盖层界面层21和栅极开口槽20中的层间绝缘膜19，并且在≤550℃的温度下进行热处理。然后，在形成覆盖整个表面的导体膜23和金属膜24之后，通过CMP方法对层间绝缘膜19上的不需要的部分进行抛光和去除，以形成设置有镶嵌结构的金属栅电极的MISFET。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2005217309A Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005217309A
公开(公告)日：2005-08-11
申请号：JP2004024301
申请日：2004-01-30
申请人： Toshiba Corp , 株式会社東芝
发明人： AKASAKA YASUSHI
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/45 , H01L29/49 , H01L29/51 , H01L29/78
CPC分类号： H01L21/823842 , H01L21/28088 , H01L21/28202 , H01L29/495 , H01L29/518 , H01L29/66545 , H01L29/7833
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can suppress a deviation in threshold voltage Vth between n-and p-type MIS FET's, and also to provide a method for manufacturing the semiconductor device.
SOLUTION: The semiconductor device comprises first and second semiconductor elements. The first semiconductor element has a first gate insulating film provided on a p-type channel region, and a first gate electrode provided on the first gate insulating film and containing first metal element and nitrogen. The second semiconductor element has a second gate insulating film provided on an n-type channel region, and a second gate electrode provided on the second gate insulating film and containing a second metal element and nitrogen. The nitrogen content of the first gate electrode is larger than that of the second gate electrode.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够抑制n型和p型MIS FET之间的阈值电压Vth的偏差的半导体器件，并且还提供一种半导体器件的制造方法。解决方案：半导体器件包括第一和第二半导体元件。第一半导体元件具有设置在p型沟道区上的第一栅极绝缘膜和设置在第一栅极绝缘膜上并包含第一金属元素和氮的第一栅电极。第二半导体元件具有设置在n型沟道区上的第二栅极绝缘膜和设置在第二栅极绝缘膜上并包含第二金属元素和氮的第二栅电极。第一栅电极的氮含量大于第二栅电极的氮含量。版权所有（C）2005，JPO＆NCIPI

8. 发明专利

JP2006108602A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006108602A
公开(公告)日：2006-04-20
申请号：JP2004354791
申请日：2004-12-08
申请人： Toshiba Corp , 株式会社東芝
发明人： AKASAKA YASUSHI , MIYAGAWA KAZUHIRO , SASAKI TAKAOKI
IPC分类号： H01L27/092 , C23C16/34 , H01L21/28 , H01L21/8238 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L29/517 , H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L29/4958 , H01L29/4966 , H01L29/7833
摘要： PROBLEM TO BE SOLVED: To form a high performance complementary MISFET by increasing both electron and hole mobilities of a MISFET using a high-k film. SOLUTION: A p well layer 2 and an n well layer 3 are formed in the front surface of a silicon substrate 1. In an n channel MISFET partitioned by an element isolation region 4; an n channel interface layer 5 without nitrogen addition, an n channel high dielectric gate insulating film 6 without the nitrogen addition, and an n channel gate electrode 7, are formed. And, an n-type source/drain diffusion layer 8 is prepared. With respect to this, in a p channel MISFET; a p channel interface layer 9 with nitrogen addition, a p channel high dielectric gate insulating film 10, and a p channel gate electrode 11, are formed. And, a p-type source/drain diffusion layer 12 is prepared. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过增加使用高k膜的MISFET的电子和空穴迁移率来形成高性能互补MISFET。解决方案：在硅衬底1的前表面中形成p阱层2和n阱层3.在由元件隔离区4分隔的n沟道MISFET中; 没有氮添加的n沟道界面层5，没有氮添加的n沟道高介电栅极绝缘膜6和n沟道栅电极7。并且，制备n型源极/漏极扩散层8。关于此，在p沟道MISFET中; 形成具有氮添加的p沟道界面层9，p沟道高介电栅极绝缘膜10和p沟道栅电极11。并且，制备p型源极/漏极扩散层12。版权所有（C）2006，JPO＆NCIPI

9. 发明专利

JP2005347631A Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005347631A
公开(公告)日：2005-12-15
申请号：JP2004167361
申请日：2004-06-04
申请人： Toshiba Corp , 株式会社東芝
发明人： AKASAKA YASUSHI
IPC分类号： H01L21/28 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To enable selective formation of a metal film or a metal compound film only on an insulating substance of a sample substrate having the insulating substance and a conductive substance mixedly present therein.
SOLUTION: In a method for forming a film containing a metal on a sample substrate having a conductive substance and an insulating substance mixedly present therein, an organic compound is first adsorbed on the conductive substance. An organic metal compound is then adsorbed on the insulating substrate. And a reducing agent is supplied which causes the organic compound adsorbed on the conductive substance to desorb and reduces the organic metal compound, thus depositing a film containing a metal.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：仅在具有绝缘物质的混合存在的绝缘物质和导电物质的绝缘物质上选择性地形成金属膜或金属化合物膜。解决方案：在具有导电物质和混合存在于其中的绝缘物质的样品基板上形成含有金属的膜的方法中，首先将有机化合物吸附在导电物质上。然后将有机金属化合物吸附在绝缘基板上。并且提供还原剂，其使吸附在导电物质上的有机化合物解吸并还原有机金属化合物，从而沉积含有金属的膜。版权所有（C）2006，JPO＆NCIPI

10. 发明专利

JP2004193629A Semiconductor device and method of manufacturing the same 有权
公开(公告)号：JP2004193629A
公开(公告)日：2004-07-08
申请号：JP2004061047
申请日：2004-03-04
申请人： Toshiba Corp , 株式会社東芝
发明人： AKASAKA YASUSHI , NAKAJIMA KAZUAKI , MIYANO KIYOTAKA , SUGURO KYOICHI
IPC分类号： H01L21/28 , H01L21/3205 , H01L23/52 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing the same capable of preventing the surface of a metal film from deteriorating or the like. SOLUTION: The method of manufacturing the semiconductor device has a process where at least a silicon film 16 and a metal film 18 are formed on the main surface side of a semiconductor substrate 11 and a process where an oxide film 21 is selectively formed on the surface of the silicon film by treating the semiconductor substrate on which the silicon film and the metal film are formed in a gas atmosphere which oxidizes the silicon and does not oxidize the metal film. COPYRIGHT: (C)2004,JPO&NCIPI

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