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1. 发明专利

JP2009016390A Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：JP2009016390A
公开(公告)日：2009-01-22
申请号：JP2007173180
申请日：2007-06-29
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUDERA KATSUKI
IPC分类号： H01L21/822 , H01L27/04
CPC分类号： H03K19/0005 , H03F1/56 , H03F3/45183 , H03F2200/222 , H03F2200/387 , H03F2203/45691
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of accurately measuring the resistance value of a terminating resistor by removing the influence of the contact resistance and capable of preventing the increase of the area occupied thereby. SOLUTION: This semiconductor integrated circuit comprises at least a control signal generating circuit 41 configured as follows. When the control circuit is in a first state ST1-1, it sets first and fifth control signals ENPb, VBS at a first voltage level and sets the second, third, fourth control signals ENNb, qb, q at a second voltage level. When it is in a second state ST1-2, it makes the first to fourth control signals ENPb, ENNb, qb, q be at a second voltage level, and makes the fifth control signal VBS be at an arbitrary voltage level. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够通过消除接触电阻的影响来精确地测量终端电阻器的电阻值的半导体集成电路，并且能够防止由此占据的面积的增加。解决方案：该半导体集成电路至少包括如下配置的控制信号发生电路41。当控制电路处于第一状态ST1-1时，将第一和第五控制信号ENPb，VBS设置在第一电压电平，并将第二，第三，第四控制信号ENNb，qb，q设置在第二电压电平。当处于第二状态ST1-2时，使第一至第四控制信号ENPb，ENNb，qb，q处于第二电压电平，并使第五控制信号VBS处于任意电压电平。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2010041275A Pll circuit 审中-公开
标题翻译： PLL电路
公开(公告)号：JP2010041275A
公开(公告)日：2010-02-18
申请号：JP2008200487
申请日：2008-08-04
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUDERA KATSUKI
IPC分类号： H03L7/099 , H03B5/12 , H03K3/03 , H03K3/354 , H03L7/093
CPC分类号： H03L7/0995 , H03L7/0893 , H03L7/093 , H03L7/099 , H03L2207/06
摘要： PROBLEM TO BE SOLVED: To provide a PLL (Phase Locked Loop) circuit for reducing a jitter of an output clock while maintaining an oscillation frequency range of a voltage control oscillation circuit wide without complicating a circuit or control. SOLUTION: The PLL circuit includes a VCO circuit 4a which generates an output clock having a frequency corresponding to potential of a control voltage signal input VCTRL input from an LPF 3 at a pre-stage by using a ring oscillator in which M delay circuits having delay times changing according to a control voltage to be input to a control terminal are connected in a ring shape. The VCO circuit 4a includes a low-pass filter which extracts a control voltage signal VCTRL in a low frequency band from the control voltage signal VCTRL and, in the ring oscillator, the control voltage signal VCTRL is input to control terminals of m (m COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于减小输出时钟的抖动的PLL（锁相环）电路，同时保持电压控制振荡电路的振荡频率范围宽而不使电路或控制复杂化。解决方案：PLL电路包括VCO电路4a，该VCO电路4a通过使用环形振荡器产生具有对应于从LPF 3输入的控制电压信号输入VCTRL的电位的频率的输出时钟，所述环形振荡器的M延迟具有根据要输入到控制端子的控制电压而具有延迟时间变化的电路连接成环形。 VCO电路4a包括从控制电压信号VCTRL提取低频带中的控制电压信号VCTRL的低通滤波器，并且在环形振荡器中，控制电压信号VCTRL被输入到m（m < M个延迟电路和控制电压信号VCTRL 2中的M个延迟电路输入到各个（Mm）个延迟电路的控制端子。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2006277867A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2006277867A
公开(公告)日：2006-10-12
申请号：JP2005097936
申请日：2005-03-30
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO MIKIHIKO , MATSUDERA KATSUKI
IPC分类号： G11C29/56 , G01R31/28 , G11C11/401
CPC分类号： G11C7/1036 , G11C7/1039 , G11C7/1051 , G11C7/106 , H03K3/356139
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device which can check its input and output function and reduce the check cost even when using an inexpensive checker which has input and output speed slower than its own data input and out put speed.
SOLUTION: A data multiplexer 11 has a plurality of input parallel data lines and a plurality of output parallel data lines and switches its outputting states according to the control signals: that is, the state of outputting the parallel data that are read from the memory core section 2 and inputted into the plurality of parallel data lines to the plurality of output parallel data lines corresponding respectively, and the state of selecting 1-bit data from the parallel data that are inputted into the plurality of input parallel data lines to output to plurality of the output parallel data lines. The data outputted from the data multiplexer 11 are converted by the shift register 8 and the output data buffer circuit 9 into the serial data, and outputted to the external data line pair DQ/bDQ by the output drive circuit 10.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以检查其输入和输出功能并降低检查成本的半导体存储器件，即使当使用具有比其自身数据输入和输出速度慢的输入和输出速度的廉价检查器时。解决方案：数据多路复用器11具有多条输入并行数据线和多条输出并行数据线，并根据控制信号切换其输出状态：即输出从存储器核心部分2并分别输入到分别对应的多个输出并行数据线的多条并行数据线中，以及从输入到多条输入并行数据线的并行数据中选择1位数据的状态，输出到多个输出并行数据线。从数据多路复用器11输出的数据由移位寄存器8和输出数据缓冲电路9转换为串行数据，并通过输出驱动电路10输出到外部数据线对DQ / bDQ。版权所有：（C）2007，JPO＆INPIT

4. 发明专利

JP2013070345A Pll circuit 审中-公开
标题翻译： PLL电路
公开(公告)号：JP2013070345A
公开(公告)日：2013-04-18
申请号：JP2011209250
申请日：2011-09-26
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUDERA KATSUKI
IPC分类号： H03L7/093 , H03L7/08 , H03L7/10
摘要： PROBLEM TO BE SOLVED: To provide a PLL circuit capable of reducing jitter of an output clock while widely maintaining the oscillation frequency range of a voltage-controlled oscillation circuit.SOLUTION: A PLL circuit includes: a comparison circuit; a charge-pump circuit; and a first low-pass filter that has a resistive element having one end connected to an output of the charge-pump circuit and a capacitive element having one end connected to the other end of the resistive element and having the other end connected to the ground, converts a current outputted from the charge-pump circuit, outputs a first control voltage signal from the one end of the resistive element, and outputs a second control voltage signal from the one end of the capacitive element. The PLL circuit includes an amplifier circuit in which a first non-inverting input terminal is connected to the one end of the resistive element, a second non-inverting input terminal is connected to the one end of the capacitive element, and an output terminal and an inverting terminal are connected, and a third control voltage signal is outputted from the output terminal. The PLL circuit includes a VCO circuit that outputs an output clock with a frequency according to the third control voltage signal.
摘要翻译：要解决的问题：提供一种能够在广泛地保持压控振荡电路的振荡频率范围的同时减少输出时钟抖动的PLL电路。解决方案：PLL电路包括：比较电路; 电荷泵电路; 以及第一低通滤波器，其具有电阻元件，所述电阻元件的一端连接到所述电荷泵电路的输出端;电容元件的一端连接到所述电阻元件的另一端并且另一端连接到地转换从电荷泵电路输出的电流，从电阻元件的一端输出第一控制电压信号，并从电容元件的一端输出第二控制电压信号。 PLL电路包括放大电路，其中第一非反相输入端连接到电阻元件的一端，第二非反相输入端连接到电容元件的一端，输出端和连接反相端子，从输出端子输出第三控制电压信号。 PLL电路包括VCO电路，其输出具有根据第三控制电压信号的频率的输出时钟。版权所有（C）2013，JPO＆INPIT

5. 发明专利

JP2009284444A Voltage control oscillation circuit 审中-公开
标题翻译：电压控制振荡电路
公开(公告)号：JP2009284444A
公开(公告)日：2009-12-03
申请号：JP2008137174
申请日：2008-05-26
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUDERA KATSUKI
IPC分类号： H03K3/03 , H03K3/354 , H03L7/099
摘要： PROBLEM TO BE SOLVED: To provide a voltage control oscillation circuit which corrects a skew of output clock and reduce a fraction defective.
SOLUTION: The voltage control oscillation circuit 14 includes a first ring oscillator 21 having a plurality of steps of delay circuits which are connected circularly by connecting the final step of output and the initial step of input, a second ring oscillator 22 having a plurality of steps of delay circuits which are connected circularly by connecting the final step of output and the initial step of input. a pair of first and second inversion circuits 23-1, 23-2 which are cross-coupled to the first and second ring oscillators, a first phase composite circuit 25 which has at least a third inversion circuit whose input is connected to the output of the first ring oscillator and a fourth inversion circuit whose input is connected to the input of the final step of delay circuit of the second ring oscillator, and a second phase composite circuit 26 which has at least a fifth inversion circuit whose input is connected to the output of the second ring oscillator and a sixth inversion circuit whose input is connected to the input of the final step of delay circuit of the first ring oscillator.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供校正输出时钟的偏斜并减少部分有缺陷的电压控制振荡电路。解决方案：电压控制振荡电路14包括第一环形振荡器21，其具有通过连接输出的最后步骤和输入的初始步骤而循环连接的多个延迟电路的步骤;第二环形振荡器22，具有通过连接输出的最后步骤和输入的初始步骤循环连接的多个延迟电路的步骤。与第一和第二环形振荡器交叉耦合的一对第一和第二反相电路23-1,23-2，具有至少第三反相电路的第一相位复合电路25，其输入端连接到第一环形振荡器和第四反相电路，其输入连接到第二环形振荡器的延迟电路的最后一步的输入端，以及第二相位复合电路26，其具有至少第五反相电路，其输入端连接到第二环形振荡器的输出和第六反相电路，其输入连接到第一环形振荡器的延迟电路的最后一步的输入。版权所有（C）2010，JPO＆INPIT

6. 发明专利

JP2008028004A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2008028004A
公开(公告)日：2008-02-07
申请号：JP2006196505
申请日：2006-07-19
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO MIKIHIKO , KOYANAGI MASARU , MATSUDERA KATSUKI
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： G11C5/14 , G11C5/02 , G11C5/025 , H01L2224/48091 , H01L2224/48227 , H01L2225/06562 , H01L2924/13091 , H01L2924/15192 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that can be inexpensively manufactured by reducing a chip area of a semiconductor chip and that of a memory controller, and also that achieves relaxation in spatial restrictions between chips in a multi-chip package. SOLUTION: The semiconductor device is provided with a package substrate 11, each semiconductor chip 12, the memory controller 13 for controlling each semiconductor chip 12, and a power-supply chip 14 having a semiconductor capacitor. The semiconductor device is composed so that the semiconductor chips 12(1), 12(2) are mounted on the package substrate 11, the memory controller 13 and the power-supply chip 14 are mounted on the semiconductor chip 12(2), and the semiconductor capacitor is used for stabilizing a voltage supplied to the semiconductor chips 12(1), 12(2). COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供可以通过减少半导体芯片和存储器控制器的芯片面积而廉价地制造的半导体器件，并且还实现了在多芯片封装中的芯片之间的空间限制的放松。解决方案：半导体器件设置有封装基板11，每个半导体芯片12，用于控制每个半导体芯片12的存储器控制器13以及具有半导体电容器的电源芯片14。半导体器件被构成为使得半导体芯片12（1），12（2）安装在封装基板11上，存储器控制器13和电源芯片14安装在半导体芯片12（2）上，并且半导体电容器用于稳定提供给半导体芯片12（1），12（2）的电压。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2007102483A Semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路
公开(公告)号：JP2007102483A
公开(公告)日：2007-04-19
申请号：JP2005291472
申请日：2005-10-04
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUDERA KATSUKI
IPC分类号： G06F1/06
CPC分类号： H03L7/18 , H03L7/0995 , H04L7/033
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of generating a polyphase high frequency clock wherein phases are uniformly shifted. SOLUTION: This semiconductor integrated circuit has: a correction circuit 25a correcting phase differences and duty cycles of a first clock pair VC0, VC180 and a second clock pair VC90, VC270, correcting a phase difference between the first clock pair VC0, VC180 and the second clock pair VC90, VC270, and generating a first output clock pair CK0, CK180 and a second output clock pair CK90, CK270; and a control circuit 26a detecting the duty cycles of the first output clock pair CK0, CK180 and the second output clock pair CK90, CK270, detecting the phase difference between the first output clock pair CK0, CK180 and the second output clock pair CK90, CK270, and controlling the correction circuit 25a. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供能够产生相位均匀移位的多相高频时钟的半导体集成电路。解决方案：该半导体集成电路具有校正电路25a，用于校正第一时钟对VC0，VC180和第二时钟对VC90，VC270的相位差和占空比，校正第一时钟对VC0，VC180之间的相位差和第二时钟对VC90，VC270，并产生第一输出时钟对CK0，CK180和第二输出时钟对CK90，CK270; 以及检测第一输出时钟对CK0，CK180和第二输出时钟对CK90的占空比的控制电路26a，CK270检测第一输出时钟对CK0，CK180与第二输出时钟对CK90之间的相位差CK270 ，并且控制校正电路25a。版权所有（C）2007，JPO＆INPIT

8. 发明专利

JP2014103551A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2014103551A
公开(公告)日：2014-06-05
申请号：JP2012254582
申请日：2012-11-20
申请人： Toshiba Corp , 株式会社東芝
发明人： YAMAI SHOTARO , MATSUDERA KATSUKI
IPC分类号： H03K19/0175 , G11C16/04 , G11C16/06 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that corrects an on resistance of an input/output circuit in response to a temperature and a supply voltage during actual use.SOLUTION: The semiconductor device includes: an R/B pin 21 for outputting a signal indicative of an operational state; a DQ pin 31 for inputting/outputting data; a plurality of first MOS transistors supplied at one end of a current path with a first voltage corresponding to a voltage value of the R/B pin 21; a plurality of second MOS transistors supplied at one end of a current path with a second voltage corresponding to a voltage value of the DQ pin 31; a voltage comparison circuit CP1 for comparing the voltage value of the R/B pin 21 with a reference voltage and outputting a first comparison signal depending on the result of comparison; and a ZQ correction control circuit 17 for controlling a first number by which the plurality of first MOS transistors are turned on, on the basis of the first comparison signal, and controlling a second number by which the plurality of second MOS transistors are turned on in response to the first number.
摘要翻译：要解决的问题：提供一种半导体器件，其在实际使用期间响应于温度和电源电压来校正输入/输出电路的导通电阻。解决方案：半导体器件包括：R / B引脚21，用于输出指示操作状态的信号; 用于输入/输出数据的DQ引脚31; 多个第一MOS晶体管，其在电流路径的一端被提供有对应于R / B引脚21的电压值的第一电压; 多个第二MOS晶体管，其在电流路径的一端提供对应于DQ引脚31的电压值的第二电压; 电压比较电路CP1，用于将R / B引脚21的电压值与参考电压进行比较，并根据比较结果输出第一比较信号; 以及ZQ校正控制电路17，用于根据第一比较信号控制多个第一MOS晶体管导通的第一数量，并且控制多个第二MOS晶体管导通的第二数量回应第一个数字。

9. 发明专利

JP2012160990A Differential output buffer 有权
标题翻译：差分输出缓冲器
公开(公告)号：JP2012160990A
公开(公告)日：2012-08-23
申请号：JP2011020380
申请日：2011-02-02
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIRAI JUNICHIRO , MATSUDERA KATSUKI
IPC分类号： H03K19/0175 , H03F3/45 , H04L25/02
CPC分类号： H03K19/018528 , H04L25/0272
摘要： PROBLEM TO BE SOLVED: To reduce current fluctuations without increasing a transition time between a transmission state and a standby state.SOLUTION: A main driver 1 performs level conversion of differential signals PREP, PREN, and a bypass circuit 2 bypasses a current I3 flowing through the main driver 1 such that a change in a current I5 flowing from a high supply potential VDD to a low supply potential VSS at a transition of the main driver 1 between an operating state and a standby state is within a constant range.

10. 发明专利

JP2011155371A Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：JP2011155371A
公开(公告)日：2011-08-11
申请号：JP2010014406
申请日：2010-01-26
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUDERA KATSUKI
IPC分类号： H03K5/19 , G01R31/28 , H04L25/02 , H04L25/03
CPC分类号： H03K5/24
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of testing a squelch circuit at a higher speed using a DC voltage by a low-speed tester.
SOLUTION: In the testing operation of the squelch circuit, in the state of applying a first DC voltage to a first reception terminal and applying a second DC voltage different from the first DC voltage to a second reception terminal, the semiconductor integrated circuit controls a first switch circuit and a second switch circuit so as to synchronize ON/OFF, and also controls a third switch circuit and a fourth switch circuit so as to synchronize ON/OFF so as to complement the ON/OFF of the first and second switch circuits.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体集成电路，能够通过低速测试器使用DC电压以更高的速度测试静噪电路。解决方案：在静噪电路的测试操作中，在向第一接收端施加第一DC电压并向第二接收端施加不同于第一DC电压的第二DC电压的状态下，半导体集成电路控制第一开关电路和第二开关电路以同步ON / OFF，并且还控制第三开关电路和第四开关电路，以便同步ON / OFF，以补充第一和第二开关开关电路。版权所有（C）2011，JPO＆INPIT

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