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1. 发明专利

JP2007147410A Electronic device 审中-公开
标题翻译：电子设备
公开(公告)号：JP2007147410A
公开(公告)日：2007-06-14
申请号：JP2005341281
申请日：2005-11-25
申请人： Tektronix Japan Ltd , 日本テクトロニクス株式会社
发明人： SUGIYAMA TOSHIO , TAKAI TORU
IPC分类号： G01D7/00
CPC分类号： G01R13/029 , G01R1/025
摘要： PROBLEM TO BE SOLVED: To provide an electronic device for executing a desired operation corresponding to a program, capable of easily accessing information on a description method of a command, and providing information including a description method of a concrete set value.
SOLUTION: A command help bar 100 is provided in a window 99, and thereby descriptions 102 of a command and an argument corresponding to a user operation and information 104 relative to explanation on the description method are displayed corresponding to the user operation. In this case, since a set value input by the user is used as the argument, the user can understand a more concrete description method. A plurality of windows can be displayed on a display screen, and the descriptions of the command and the argument including the concrete set value on the command help bar 100 are copied in the window 99, and they can be used as a paste in a source code of a program under production in a programming window displayed separately. Consequently, the efficiency of a programming work can be heightened.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于执行与程序相对应的期望操作的电子设备，能够容易地访问关于命令的描述方法的信息，并且提供包括具体设定值的描述方法的信息。解决方案：在窗口99中提供命令帮助栏100，并且相应于用户操作来显示相对于关于描述方法的说明的与用户操作和信息104相对应的命令和参数的描述102。在这种情况下，由于用户输入的设定值被用作参数，所以用户可以理解更具体的描述方法。可以在显示屏幕上显示多个窗口，并且在窗口99中复制包括命令帮助栏100上的具体设置值的命令和参数的描述，并且它们可以用作源中的粘贴在编程窗口中单独显示正在生产的程序的代码。因此，可以提高编程工作的效率。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2007147337A Displaying method used for signal generating apparatus 有权
标题翻译：用于信号发生装置的显示方法
公开(公告)号：JP2007147337A
公开(公告)日：2007-06-14
申请号：JP2005339284
申请日：2005-11-24
申请人： Tektronix Japan Ltd , 日本テクトロニクス株式会社
发明人： SUGIYAMA TOSHIO , TAKAI TORU
IPC分类号： G01R13/20
CPC分类号： G01R31/2841
摘要： PROBLEM TO BE SOLVED: To give information about a progress state of a sequence to a user intelligibly, even after starting a signal output operation.
SOLUTION: A plurality of signal patterns are displayed in accordance with the sequence on a displaying device of a signal generating apparatus, and if an output starting operation of the signal patterns is carried out subsequently, a current output or output waiting signal pattern is displayed so as to be capable of being identified from other signal patterns. At this point, each signal pattern may be displayed so as to correspond to an identifier such as an index number. The identifier may be made blinking for example, in order that the identifier of the current output or output waiting signal pattern can be identified. Alternatively, the identification may be made by carrying out displaying using a color different from those of other signal patterns, for example, by reversing the color of the current output or output waiting signal pattern.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：即使在开始信号输出操作之后，也可以向用户提供关于序列的进展状态的信息。解决方案：根据信号发生装置的显示装置上的顺序显示多个信号模式，并且如果随后执行信号模式的输出开始操作，则当前输出或输出等待信号模式被显示为能够从其他信号模式识别。此时，可以显示每个信号图案，以便对应于诸如索引号的标识符。例如，可以使标识符闪烁，以便可以识别当前输出或输出等待信号模式的标识符。或者，可以通过使用与其他信号图案不同的颜色进行显示，例如通过反转当前输出或输出等待信号图案的颜色来进行识别。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2006041755A Variable delay circuit 有权
标题翻译：可变延迟电路
公开(公告)号：JP2006041755A
公开(公告)日：2006-02-09
申请号：JP2004216480
申请日：2004-07-23
申请人： Tektronix Japan Ltd , 日本テクトロニクス株式会社
发明人： TAKAI TORU
IPC分类号： H03K5/13 , H03K5/131
CPC分类号： H03K5/135 , H03K5/13 , H03K2005/00058
摘要： PROBLEM TO BE SOLVED: To update a delay time added to the rising edge or the falling edge of a pulse train being inputted more quickly than before.
SOLUTION: First and second delay paths 16 and 18 add delays depending on delay data to the rising edge or the falling edge of a pulse train being inputted. An OR circuit 46 synthesizes and outputs output signals of these delay paths. Gates 50 and 52 receive the pulse train and control pulse train supply to the first and the second delay paths 16 and 18 is controlled depending on a control signal CTRL. When a delay time set circuit 44 and the first delay path 16 are supplied with the pulse train, a gate 52 is controlled to start pulse train supply to the second delay path 18 following to the loading of the delay data to the second delay path 18 and then pulse train supply to the first delay path 16 is stopped.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：更新添加到比以前更快输入的脉冲串的上升沿或下降沿的延迟时间。解决方案：第一和第二延迟路径16和18根据延迟数据增加延迟到输入的脉冲串的上升沿或下降沿。 OR电路46合成并输出这些延迟路径的输出信号。门50和52接收脉冲串，并且根据控制信号CTRL来控制对第一和第二延迟路径16和18的控制脉冲串供给。当延迟时间设定电路44和第一延迟路径16被提供脉冲串时，控制门52以便在将延迟数据加载到第二延迟路径18之后开始向第二延迟路径18提供脉冲串然后停止向第一延迟路径16供给脉冲串。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2006300818A Signal generator, and method of displaying parameter edition screen layer 有权
标题翻译：信号发生器和显示参数编辑屏幕的方法
公开(公告)号：JP2006300818A
公开(公告)日：2006-11-02
申请号：JP2005125031
申请日：2005-04-22
申请人： Tektronix Japan Ltd , 日本テクトロニクス株式会社
发明人： SUGIYAMA TOSHIO , ADAM SUSAN C , KOMATSU HIROSHI , ITO KAZUMASA , HAYASE HIROYUKI , TAKAI TORU
IPC分类号： G01R31/3183
CPC分类号： G01R31/31917 , G01R31/31912
摘要： PROBLEM TO BE SOLVED: To enhance operability for parameter edition of an output signal in a signal generator. SOLUTION: A plurality of tabs 38, 40, 42 are displayed on a display screen 14 to indicate the existence of a plurality of parameter edition screen layers for different combinations of characters, waveforms and channels, and one of the tabs is selected out of the plurality of tabs to be switched to the corresponding parameter edition screen. The channels and the waveforms are indicated on the tabs 38, 40, 42 in response to setting, the characters and the waveforms are changed dynamically in response to change of the setting, and the setting in the present of the each channel is thereby confirmed at a glance. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提高信号发生器中输出信号参数编辑的可操作性。解决方案：在显示屏幕14上显示多个标签38,40,42，以指示用于字符，波形和通道的不同组合的多个参数编辑屏幕层的存在，并且选择一个标签在多个标签之间切换到相应的参数编辑屏幕。响应于设置，通道和波形在标签38,40,42上指示，字符和波形响应于设置的改变而动态地改变，从而在每个通道的当前设置中被确认一目了然版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2006094243A Pulse delay circuit 有权
标题翻译：脉冲延迟电路
公开(公告)号：JP2006094243A
公开(公告)日：2006-04-06
申请号：JP2004278568
申请日：2004-09-24
申请人： Tektronix Japan Ltd , 日本テクトロニクス株式会社
发明人： TAKAHASHI HISAO , TAKAI TORU
IPC分类号： H03K5/13 , H03K5/131
CPC分类号： H03K7/06 , G01R31/31709
摘要： PROBLEM TO BE SOLVED: To add a much greater jitter to a high-speed reference pulse sequence.
SOLUTION: A buffer circuit 10 outputs a non-inverted pulse and an inverted pulse upon receiving a reference pulse sequence. An LPF 12 and a comparator 16 output a pulse resulting from the delay of the rising edge of the non-inverted pulse upon receiving the non-inverted pulse from the buffer 10 circuit. Similarly, an LPF 14 and a comparator 18 output pulses resulting from the delay of the rising edge of the inverted pulse upon receiving the inverted pulse from the buffer 10 circuit. Frequency divider circuits 30 and 32 generate pulse sequences of 1/2 frequencies, respectively, upon receiving these delayed pulses. An exclusive OR circuit 34 generates exclusively ORs of these pulse sequences and output a pulse sequence resulting from the delay of the rising edge and the falling edge of the reference pulse sequence. By changing a delay amount in each of LPFs and comparators, the outputted pulse sequence contains a jitter.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为高速参考脉冲序列增加更大的抖动。解决方案：缓冲电路10在接收参考脉冲序列时输出非反相脉冲和反相脉冲。从缓冲器10电路接收到非反相脉冲时，LPF12和比较器16输出由非反相脉冲的上升沿的延迟导致的脉冲。类似地，当从缓冲器10电路接收到反相脉冲时，LPF 14和比较器18输出由反相脉冲的上升沿的延迟引起的脉冲。分频器电路30和32分别在接收到这些延迟的脉冲时产生1/2频率的脉冲序列。异或电路34产生这些脉冲序列的独占OR，并输出由参考脉冲序列的上升沿和下降沿的延迟导致的脉冲序列。通过改变每个LPF和比较器中的延迟量，输出的脉冲序列包含抖动。版权所有（C）2006，JPO＆NCIPI

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