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1. 发明专利

JPH0963966A VAPOR GROWTH DEVICE 失效
公开(公告)号：JPH0963966A
公开(公告)日：1997-03-07
申请号：JP21596595
申请日：1995-08-24
申请人： TOSHIBA MICRO ELECTRONICS , TOSHIBA CORP
发明人： TANAKA KAZUHIRO , HOSHI TADAHIDE
IPC分类号： C30B25/12 , H01L21/205
摘要： PROBLEM TO BE SOLVED: To provide a vapor growth device of a structure, wherein a crack or a break in a wafer, a slip on the wafer, particles of the wafer and the like can be prevented from being generated and a film thickness, which is superior in uniformity, can be formed. SOLUTION: A vapor growth device is provided with a rotatable susceptor 5 having an overhang-shaped wafer placement part 20, which is recessed so as to coincide with the shape of a semiconductor wafer and places and supports the peripheral part of the wafer, a first heater 8, which heats a prescribed radial region from the position of the center of the lower surface of the wafer, which is placed on the part 20, and a second heater 9, which is positioned under the part 20 and heats indirectly the periphery of the wafer via the part 20. An orientation flat placement part 20a, on which an orientation flat part 6a on the part 20 is positioned, is formed so that the heat capacity of the part 20a is reduced compared with that of the part of the part 20 other than this part 20a.

2. 发明专利

JPH08227994A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH08227994A
公开(公告)日：1996-09-03
申请号：JP752895
申请日：1995-01-20
申请人： TOSHIBA MICRO ELECTRONICS , TOSHIBA CORP
发明人： HOSHI TADAHIDE , NITTA SHINICHI , SAITO YOSHIHIKO , TSUKANO KENICHI , AKITA KEIKO
IPC分类号： C30B29/06 , H01L21/336 , H01L29/78 , H01L29/786
摘要： PURPOSE: To provide a manufacturing method for semiconductor devices whereby single crystalline silicon films excellent in selectivity are grown at a high growing speed, and a manufacturing method for semiconductor devices whereby excellent single crystalline silicon films and excellent polycrystalline silicon films or amorphous silicon films can be grown selectively. CONSTITUTION: This concerns a manufacturing method having an oxide film forming process for forming an oxide film 22 on a silicon substrate 21, an oxide film opening process for providing an opening 22a in the oxide film 22 and exposing a part of the silicon substrate 21, and a single crystalline silicon film forming process for forming a single crystalline silicon film 23 on the silicon substrate 21 exposed, and the single crystalline silicon film forming process is a process which performs the vapor growth of a silicon deposited layer rotating the silicon substrate 21 at 500rpm or more under a reduced pressure atmosphere less than 13,000Pa. Besides, the vapor growth of a polycrystalline silicon film or amorphous silicon film is performed rotating the silicon substrate 21 at 500rpm or less under an atmosphere of pressure higher than the single crystalline silicon film forming process.

3. 发明专利

JPH1050615A SINGLE WAFER PROCESSING GAS-PHASE GROWTH DEVICE 失效
公开(公告)号：JPH1050615A
公开(公告)日：1998-02-20
申请号：JP20036396
申请日：1996-07-30
申请人： TOSHIBA MICRO ELECTRONICS , TOSHIBA CORP
发明人： TANAKA KAZUHIRO , HOSHI TADAHIDE , OGINO MASANOBU
IPC分类号： C30B25/14 , H01L21/205 , H01L21/22
摘要： PROBLEM TO BE SOLVED: To significantly reduce sticking of reaction by-products to the side surface of a reaction vessel. SOLUTION: Auxiliary gas B comprising hydrogen gas or inactive gas flows out from an inclined through tube 17 to the inside of a reaction vessel 1 and then flows downward along the side surface of the reaction vessel 1. A wafer 7 is rotated rapidly by a wafer mount part 8. A reaction gas A, flowing out of the outside periphery pat of the wafer 7 in fast rotation, advances to the side surface of the reaction vessel 1. However, the reaction gas A, heading for the side surface of the reaction vessel 1, is blocked by the auxiliary gas B flowing its side surface, resulting in almost no contact to the side surface of the reaction vessel 1. Thus, the amount of reaction bi-products sticking to the side surface of the reaction vessel 1 is significantly reduced.

4. 发明专利

JPH04330725A MANUFACTURE APPARATUS OF SEMICONDUCTOR SUBSTRATE 失效
公开(公告)号：JPH04330725A
公开(公告)日：1992-11-18
申请号：JP5264391
申请日：1991-03-18
申请人： TOSHIBA CORP , TOSHIBA MICRO ELECTRONICS
发明人： HOSHI TADAHIDE , TANAKA KAZUHIRO
IPC分类号： H01L21/304
摘要： PURPOSE:To make the thickness of a device formation layer definite without being influenced by an irregularity in blank substrates and by an irregularity in the working operation of a lapping machine by a method wherein tip parts of a plurality of claw members are inserted into gaps at pasted peripheral edge parts and their postures are fixed respectively by means of fixation jigs. CONSTITUTION:Tip parts 13 of a plurality of claw members 10 are inserted into gaps bW in peripheral edge parts of a substrate W; their postures are fixed respectively by means of fixation jigs 9; and the tip parts 13 are positioned with reference to the interface SW between blank substrates w1, w2 in individual positions regarding the circumferential direction of the twolayer substrate W. Thereby, the position of the interface SW is captured spatially. Protrusions 22 are installed at the claw members 10; a polishing operation is performed until the approach of a rotary machine (a lapping machine) 3 to the two-layer substrate W is stopped by the protrusions 22. A working operation is performed in such a way that the w1 used as a device formation layer is left only by a definite amount; the device formation layer in a definite thickness over the whole face can be obtained without being influenced by an irregularity in the blank substrates w1, w2 and in the working operation of the lapping machine.

5. 发明专利

JPH03181146A MANUFACTURE OF SEMICONDUCTOR SUBSTRATE 失效
公开(公告)号：JPH03181146A
公开(公告)日：1991-08-07
申请号：JP31892889
申请日：1989-12-11
申请人： TOSHIBA CORP , TOSHIBA MICRO ELECTRONICS
发明人： HOSHI TADAHIDE , HASHIMOTO MASANORI , TANAKA KAZUHIRO
IPC分类号： H01L21/762 , H01L21/20 , H01L21/324 , H01L21/76
摘要： PURPOSE:To flatten a wafer surface and improve processing accuracy by depositing polycrystal silicon at a low temperature, embedding an isolation groove completely and then annealing at a temperature higher than the deposition temperature to suppress a warp. CONSTITUTION:A silicon dioxide film 12 is interposed and adhered between silicon wafers 111, 112 and a device side is ground to a position of a required thickness 13. Then device isolation is done by means of anisotropic etching to form an isolation groove 15, which is to be covered with silicon dioxide 14 to have a silicon island 113 completely isolated. Then deposition of polycrystal silicon 16 is performed at a temperature that uniformity of deposition speed can be maintained, subsequently annealing is done at a temperature higher than that at the time of embedding the polycrystal silicon 16 and the surface is ground to a position of a thickness 17. By thus performing two-stage heat treatment to reduce the warp of a wafer, the warp and defective deposition can be simultaneously eliminated so that a surface of the wafer can be flattened improving processing accuracy.

6. 发明专利

JPH09283529A MANUFACTURE AND INSPECTION OF SEMICONDUCTOR SUBSTRATE 失效
公开(公告)号：JPH09283529A
公开(公告)日：1997-10-31
申请号：JP3211197
申请日：1997-02-17
申请人： TOSHIBA MICRO ELECTRONICS , TOSHIBA CORP
发明人： MIYASHITA MORIYA , OGINO MASANOBU , HOSHI TADAHIDE , NUMANO MASAKUNI , SAMATA SHUICHI , SEKIHARA AKIKO , AKITA KEIKO
IPC分类号： H01L21/66 , H01L21/322
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor substrate which denuded zone(DZ) layer deep enough to prevent adverse influences to device characteristics is formed while avoiding a high-temperature annealing process at the time of manufacturing a semiconductor device with use wafer, and also to provide a method for suitably inspecting a density of oxygen precipitation (BMD) in the semiconductor substrate. SOLUTION: In the semiconductor substrate manufacturing method, oxygen precipitation nuclei are precipitated for a silicon single crystal having a region containing a first concentration of boron exceeding a predetermined value within a predetermined region on one major surface side, or oxygen precipitations are grown from the oxygen precipitation nuclei. Next, the substrate is annealed in a temperature range which is higher than a temperature of a first annealing step, sufficiently higher to reduce the oxygen precipitation nuclei or the oxygen precipitations grown therefrom and sufficiently lower to such an extent that boron re-distribution does not affect the oxygen precipitations to form a predetermined depth of denuded layer within the predetermined zone on one major surface side. The semiconductor substrate inspecting method further includes a step of measuring a density of odes of the oxygen precipitations grown from the oxygen precipitation nuclei precipitated within the silicon single crystal, following the above annealing process.

7. 发明专利

JPH02273923A MANUFACTURE OF SEMICONDUCTOR SUBSTRATE 失效
公开(公告)号：JPH02273923A
公开(公告)日：1990-11-08
申请号：JP9693189
申请日：1989-04-17
申请人： TOSHIBA CORP , TOSHIBA MICRO ELECTRONICS
发明人： HOSHI TADAHIDE , TANAKA KAZUHIRO
IPC分类号： H01L21/02 , H01L21/304
摘要： PURPOSE:To contrive the prevention of the generation of a break, a crack and the like in the outer peripheral part of a wafer by a method wherein the diameter of a first wafer is left without being changed and at the same time, the unbonded outer peripheral part, at which the first wafer and a second wafer oppose to each other pinching a void between them, of the wafer is removed. CONSTITUTION:A bonded semiconductor substrate (a bonded wafer) 14 is formed by a method wherein the fellow mirror-polished main surfaces of first and second semiconductor substrates (first and second wafers) 11 and 12 performed a bevel work 16 on their sidewalls are closely adhered to each other, are heat-treated and are integrally formed, and a joined semiconductor substrate 15 is formed by a method wherein the fellow main surfaces, which are mirror- polished and on the main surface of a first semiconductor substrate 11a on at least one side of which an oxide film 13 is applied, of the first substrate 11a and a second semiconductor substrate 12, which are performed a bevel work 16 on their sidewalls, are closely adhered to each other, are heat-treated and are integrally formed. The diameter of the substrate 11 of the substrate 14 is left without being changed and at the same time, the sidewall of the substrate 14 is ground so that an unbonded outer peripheral part, at which the substrates 11 and 12 oppose to each other pinching a void between them, does not exist. In such a way, the unbonded outer peripheral part, that is, the outer peripheral part, at which the first and second wafers oppose to each other pinching a void between them, is removed. Thereby, a supply of the bonded wafer, in which a break, a crack and the like are not generated in its outer peripheral part, becomes possible.

8. 发明专利

JP2005311111A Semiconductor device and its fabrication process 审中-公开
标题翻译：半导体器件及其制造工艺
公开(公告)号：JP2005311111A
公开(公告)日：2005-11-04
申请号：JP2004126842
申请日：2004-04-22
申请人： Toshiba Corp , 株式会社東芝
发明人： YONEMURA KOJI , HOSHI TADAHIDE
IPC分类号： H01L21/331 , H01L21/764 , H01L27/08 , H01L29/732 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having an element isolation structure capable of reducing the parasitic capacitance of a transistor remarkably.
SOLUTION: The semiconductor device includes an element isolation insulating film 14 formed on the surface of a semiconductor substrate to surround an element region on the plane of the semiconductor substrate 11. A first cavity region 13a is formed in the semiconductor substrate beneath the element region and has a planar shape. A second cavity region 13b extends from the bottom part of the element isolation insulating film to the same depth as the first cavity region in the cross-section of the semiconductor substrate and surrounds the element region on the plane.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有能够显着降低晶体管的寄生电容的元件隔离结构的半导体器件。解决方案：半导体器件包括形成在半导体衬底的表面上以围绕半导体衬底11的平面上的元件区域的元件隔离绝缘膜14.第一空腔区域13a形成在半导体衬底的下方元件区域并具有平面形状。第二空腔区域13b从元件隔离绝缘膜的底部延伸到与半导体衬底的横截面中的第一空腔区域相同的深度并且围绕该平面上的元件区域。版权所有（C）2006，JPO＆NCIPI

9. 发明专利

JPH05198514A SINGLE WAFER EPITAXIAL GROWTH DEVICE 失效
公开(公告)号：JPH05198514A
公开(公告)日：1993-08-06
申请号：JP782892
申请日：1992-01-20
申请人： TOSHIBA CORP
发明人： HOSHI TADAHIDE
IPC分类号： H01L21/205 , H01L21/677 , H01L21/68 , H01L21/683
摘要： PURPOSE:To increase the throughput remarkably by conducting epitaxial growth processes continuously. CONSTITUTION:An orientation flat of a semiconductor substrate 4 is positioned in a specified place by a positioning device 6 and then the semiconductor substrate 4 is centered. After that, the substrate 4 is carried right above a susceptor 16 by means of a carrying mechanism 7. The rotational position of the susceptor 16 is preliminarily reset to the original position by a resetting mechanism. A wafer chuck table 18 goes up and receives the semiconductor substrate 4 from the carrying mechanism 7 and then goes down to mount the semiconductor substrate 4 on the susceptor 16. Since the semiconductor substrate 4 is positioned and the susceptor 16 is reset to the original position, the semiconductor substrate 4 is mounted at the same place on the susceptor 16 at all times. After that, a reaction container 1 is covered and then the epitaxial growth process is conducted.

10. 发明专利

JPS63314825A MANUFACTURE OF SEMICONDUCTOR SUBSTRATE 失效
公开(公告)号：JPS63314825A
公开(公告)日：1988-12-22
申请号：JP15028287
申请日：1987-06-18
申请人： TOSHIBA CORP
发明人： HOSHI TADAHIDE
IPC分类号： H01L29/68 , H01L21/02 , H01L21/18 , H01L21/20 , H01L21/265 , H01L21/324 , H01L21/336 , H01L29/739 , H01L29/78
摘要： PURPOSE:To increase the conductivity modulation effect of a substrate, and make the substrate suitable for an insulated gate bipolar transistor substrate of high breakdown voltage, by controlling the impurity concentration profile in the vicinity of bonding boundary surface, when a bonding semiconductor substrate is manufactured. CONSTITUTION:For a semiconductor substrate 1, a P type Si substrate whose resistivity is smaller than or equal to 0.02OMEGAcm is used, and thereon an N type Si substrate 3 whose resistivity is larger than or equal to 10OMEGAcm is bonded. On the surface bonded to the substrate 1, an N type layer 2 being a P ion implanted layer of 2X1015atm/cm is formed. After the surface of the layer 2 is cleaned, it made to abut on the substrate 1, and subjected to heat treatment for bonding at a temperature of 1100 deg.C in N2 for 2 hours. After that, this laminated substrate is subjected to profile controlling heat treatment in N2 which is more than or equal to 1100 deg.CX16 hours or 1200 deg.CX1 hour. Thereby, the conductivity modulation effect between substrates is increased.

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