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1. 发明专利

JPH06310528A MANUFACTURE OF MOS TYPE SEMICONDUCTOR DEVICE OF MASK LDD STRUCTURE 失效
公开(公告)号：JPH06310528A
公开(公告)日：1994-11-04
申请号：JP32753193
申请日：1993-12-24
申请人： TOSHIBA CORP , TOSHIBA MICRO ELECTRONICS
发明人： ATSUMI SHIGERU , SAITO SHINJI , TANAKA SUMIO , OTSUKA NOBUAKI , YOSHIKAWA KUNIYOSHI , KAMEI TAKASHI
IPC分类号： H01L21/336 , H01L29/78 , H01L29/784
摘要： PURPOSE:To provide a manufacturing method for a MOS type semiconductor device of mask LDD structure wherein electrical characteristic dispersion is not generated between a plurality of transistors. CONSTITUTION:A field insulation film 24 is formed on a P-type substrate 11, gate electrodes 17, 17 are formed and semiconductor regions 25, 26, 27 are formed by diffusing N-type impurities at a low concentration into the substrate 11 by using the field insulation film 24 and the gate electrodes 17, 17 as a mask. Photoresist films 28, 28 are selectively made to remain to cover a part of the semiconductor region 25 at the side of the gate electrode 17 and a part of the semiconductor region 27 at the side of the gate electrode 17, and N-type impurities are diffused into the substrate 11 at a high concentration to form high concentration drain regions 12, 14 inside the semiconductor region 25 and inside the semiconductor region 27. The semiconductor region 25 and the semiconductor region 27 which are covered with the photoresist films 28, 28 are made to remain as low concentration drain regions 18, 19.

2. 发明专利

JPH0629547A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH0629547A
公开(公告)日：1994-02-04
申请号：JP18092292
申请日：1992-07-08
申请人： TOSHIBA CORP
发明人： YOSHIKAWA KUNIYOSHI
IPC分类号： G11C17/00 , H01L21/8247 , H01L27/108 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , G11C16/02 , G11C16/04
摘要： PURPOSE:To increase capacitance between first and second electrodes and reduce writing voltage without deteriorating element characteristics. CONSTITUTION:A second polycrystalline silicon film 31 is deposited on a first gate insulation film 31, a first side wall material 29, and a third oxide film 26 and then a fifth oxide film 32 is formed on the second polycrystalline silicon film 31. A sixth oxide film 34 is deposited on a second silicon nitride film 33. A second silicon nitride film 35, the sixth oxide film 34, the second silicon nitride film 33, the fifth oxide film 32, and the second polycrystalline silicon film 31 are patterned by the photoetching method, thus forming the first gate electrode 36 and the second gate insulation film 34. A fourth polycrystalline silicon film 41 is deposited inside first and second contact holes 39 and 40 and on the third polycrystalline silicon film 35 and a second side wall material 38, thus forming a second gate electrode 42 and hance increasing the capacitance between the first and second gate electrodes.

3. 发明专利

JPH0370179A NONVOLATILE MEMORY DEVICE 失效
公开(公告)号：JPH0370179A
公开(公告)日：1991-03-26
申请号：JP20473489
申请日：1989-08-09
申请人： TOSHIBA CORP
发明人： YOSHIKAWA KUNIYOSHI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To increase punch-through breakdown strength, reduce leakage current on a junction surface, and achieve miniaturization by providing a groove at a semiconductor device and forming an offset gate electrode part within the groove. CONSTITUTION:Drain diffusion layers 102 of a memory cell and a source diffusion layer 104 which is formed within a groove 103 and at the bottom of the groove are provided on the surface of a P-type silicon substrate 101. A first gate oxide film 105 is formed on the surface of the silicon substrate from the edge part of the drain diffusion layer 102 to the upper edge of the groove and a floating gate electrode 106 is formed through it. A second gate insulating film 107 is formed on this floating gate electrode 106, a third gate insulating film 117 is formed on the wall at the groove side, and a control gate electrode 108 is formed through these second and third gate insulating films 107 and 117. A CVD oxide film 109 is formed covering these, a BPSG film 110 is formed on the entire surface, a contact hole is provided on a drain diffusion layer 102, and a bit wire 111 is connected to the drain diffusion layer 102.

4. 发明专利

JPH02187994A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH02187994A
公开(公告)日：1990-07-24
申请号：JP621389
申请日：1989-01-13
申请人： TOSHIBA CORP
发明人： MIYAMOTO JUNICHI , OTSUKA NOBUAKI , YOSHIKAWA KUNIYOSHI , MORI SEIICHI
IPC分类号： G11C17/00 , G11C16/06 , G11C16/10 , G11C16/30
摘要： PURPOSE:To contrive the obviation of deterioration of data caused by a voltage stress by reducing a power supply voltage for writing data and applying it to a drain of a memory cell. CONSTITUTION:When a memory cell 13 is selected at the time of writing data, a high voltage VPP outputted from an address use buffer 19 is outputted to a control gate of the cell 13. On the other hand, from a write control use buffer 16, a voltage VPP is outputted, a voltage of (VPP'-Vth) is supplied to a Y selector through a transistor 15 and applied to a drain of the cell 13 and write of data is executed. By setting a voltage value applied to a drain of a non- selective memory cell to above a drain voltage which does not spoil a write characteristic, it does not occur that a read-out speed decreases and a write speed deteriorates, and the deterioration of data caused by a voltage stress to the non-selective memory cell can be obviated.

5. 发明专利

JPH01251759A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH01251759A
公开(公告)日：1989-10-06
申请号：JP7887988
申请日：1988-03-31
申请人： TOSHIBA CORP
发明人： YOSHIKAWA KUNIYOSHI
IPC分类号： H01L21/8247 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PURPOSE:To simply write a piece of information on manufacture for permanent preservation into a memory cell by installing a nonvolatile memory cell composed of ultraviolet-ray absorbing conductive film which is connected to a source wiring part or a drain wiring part. CONSTITUTION:A thin insulating film 5 of 500Angstrom or lower is deposited and formed in such a way that it covers the surface of a memory cell composed of a floating gate type MOS transistor of a two-layer polycrystalline silicon structure. A contact hole for drain use is made in this insulating film 5; after that, a conductive film 4 composed of polycrystalline silicon containing an N-type impurity is formed. A data line 8 using, e.g., aluminum is formed on an interlayer insulating film 13 in such a way that it comes into contact with the conductive film 4 through the contact hole. In the memory cell of this structure, even when ultraviolet rays are incident on the thin insulating film 5 between the conductive film 4 and the surface of a substrate from a peripheral part, the rays are attenuated; it is possible to simply write a piece of information on manufacture for permanent preservation use into this memory cell.

6. 发明专利

JPH01179431A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01179431A
公开(公告)日：1989-07-17
申请号：JP103088
申请日：1988-01-06
申请人： TOSHIBA CORP
发明人： YOSHIKAWA KUNIYOSHI
IPC分类号： H01L21/76
摘要： PURPOSE:To form an element isolating region in the dimension as designed thereby avoiding the disconnection of wiring etc., by a method wherein, after implanting oxygen ion, an element isolating oxide film is formed in a semiconductor substrate. CONSTITUTION:After forming a surface protective film 12 on the main surface of a semiconductor substrate 11, the first masking material 13 is formed on the protective film 12. The second masking material 14 is formed on the first masking material 13 and then both of the masking materials 13, 14 are selectively removed by anisotropical etching process. The substrate 11 is implanted with oxygen ion using the third masking material 16 as a mask only on the sidewall parts of the pattern comprising the masking materials 13, 14. The masking materials 14, 16 are removed and after converting the oxygen ion implanted region into an oxide film 18 by annealing process, the masking material 13 and the protective film 12 are removed. Through these procedures, an element isolating region in narrow width can be formed in the dimension as designed to avoid the disconnection of wiring etc.

7. 发明专利

JPS6453577A NONVOLATILE SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS6453577A
公开(公告)日：1989-03-01
申请号：JP21077487
申请日：1987-08-25
申请人： TOSHIBA CORP
发明人： YOSHIKAWA KUNIYOSHI
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To realize a substantially fine structure by a method wherein floating gate electrodes and control gate electrodes are provided on the side walls of a trench formed in a substrate and, further, source or drain regions are provided on the surface of the substrate and a drain or source region is provided on the bottom of the trench. CONSTITUTION:Floating gate electrodes are provided on a pair of facing vertical side walls in a trench formed in a P-type silicon substrate 10 and, further, control gate electrodes are provided on the floating gate electrodes. Thus, two sets of the floating gate electrodes and the control electrodes are provided on the vertical side walls of the trench. N-type diffused regions 12 provided on the substrate 10 are used as the source regions of two nonvolatile transistors and an N-type diffused region 21 formed on the bottom of the trench is used as the common drain region of the two nonvolatile transistors. The N-type diffused region 21 is connected to an electrode 23 with a polycrystalline silicon film 20. In other words, two nonvolatile transistors are formed in the trench. Moreover, as the source regions and the drain region are separated from each other along the depth direction of the trench, the possibility of creation of a leakage current accompanying the planar fine structure of an element can be avoided. Therefore, the size of the element can be substantially reduced and a substantially fine structure can be realized.

8. 发明专利

JPS6312176A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6312176A
公开(公告)日：1988-01-19
申请号：JP15497686
申请日：1986-07-03
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG
发明人： MORITA SHIGERU , YOSHIKAWA KUNIYOSHI , KAGAMI SHOICHI , KINUGAWA MASAAKI , ASAMI TETSUYA
IPC分类号： H01L21/8247 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PURPOSE:To shorten writing time, by crossing a gate electrode and a region between a source and a drain at an acute angle in a channel region between the source and drain regions. CONSTITUTION:A channel region 12 crosses an element region 3 between a source and a drain at an acture angle. Since the channel region 12 is formed in the oblique direction, the substantiel width of the effective channel becomes wide even if the width of the element region 3 is equal. Therefore a large amount of a drain current can be made to flow. In this way, an electric field is readily concentrated between drain regions 5 and 7 and a channel region 12 in the vicinity of a field insulating film 2 in the channel region 12. This is advantageous for an EPROM, which is operated by utilizing avalanche injection. The length of the side surface of a gate electrode, which passes on the element region 3, increases in comparison with a conventional type. Therefore, a region, in which electric charge is injected, is increased, and writing characteristics are improved.

9. 发明专利

JPS59217370A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS59217370A
公开(公告)日：1984-12-07
申请号：JP9266883
申请日：1983-05-26
申请人： Toshiba Corp
发明人： NAGAKUBO YOSHIHIDE , YOSHIKAWA KUNIYOSHI
IPC分类号： H01L21/8247 , H01L29/788 , H01L29/792 , H01L29/78
CPC分类号： H01L29/7885
摘要： PURPOSE:To enhance the characteristic of holding charges by a method wherein a non single crystal Si film is deposited after forming a thermal oxide film on the exposed surfaces of a floating gate electrode and a control gate electrode, thus being left only on the side surface of each insulation film, and converted into a thermal oxide film at the time forming source and drain regions. CONSTITUTION:After forming an element isolation film 22 on the surface of a P type Si substrate 21, the control gate electrode 23, a gate oxide film 24, the floating gate electrode 25 and a gate oxide film 26 are formed. Next, the thermal oxide film 27 is formed on the surfaces of the electrode 23, 25 and the substrate 21. Then, a polycrystalline Si film 28' is deposited over the entire surface and thereafter removed by etching by the film thickness, thus forming a remnant polycrystalline Si film 28'. The source region 29 and the drain region 30 are formed by ion implantation to the substrate 21. At this time, the film 28' is converted into a thermal oxide film 31, and said oxide film grows out of the surfaces of the electrodes 23, 25 and the substrate 25. After depositing a PSG film 32 over the entire surface, holes are opened, and Al films 34 and 34 are formed. The present system enables to improved the characteristic of holding charges.
摘要翻译：目的：为了通过在浮置栅电极和控制栅电极的露出表面上形成热氧化膜之后沉积非单晶硅膜的方法来提高保持电荷的特性，因此仅留在侧表面并在形成源极和漏极区域时转换成热氧化膜。构成：在P型Si衬底21的表面上形成元件隔离膜22之后，形成控制栅电极23，栅氧化膜24，浮栅电极25和栅氧化膜26。接下来，在电极23,25和基板21的表面上形成热氧化膜27.然后，在整个表面上沉积多晶Si膜28'，然后通过蚀刻除去膜厚，从而形成剩余多晶Si膜28'。源极区域29和漏极区域30通过离子注入形成到基板21.此时，膜28'被转换成热氧化膜31，并且所述氧化膜从电极23的表面生长， 25和基板25.在整个表面上沉积PSG膜32之后，打开孔，并形成Al膜34和34。本系统能够提高保持电荷的特性。

10. 发明专利

JP2001156188A SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME 失效
公开(公告)号：JP2001156188A
公开(公告)日：2001-06-08
申请号：JP2000057642
申请日：2000-03-02
申请人： TOSHIBA CORP
发明人： YOSHIKAWA KUNIYOSHI
IPC分类号： H01L21/8247 , G11C11/56 , G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device for storing information for plural bits, using a simple cell structure. SOLUTION: In this new structure of a nonvolatile semiconductor storage device for storing information for plural bits, the edge part of a gate electrode is provided with a charge-storing layer 4 for storing electrons. Thus, information on plural bits can be stored by storing the electrons in the charge storage layer 4.

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