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1. 发明专利

JPS63177546A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63177546A
公开(公告)日：1988-07-21
申请号：JP929387
申请日：1987-01-19
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG
发明人： KINUGAWA MASAAKI , ASAMI TETSUYA
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To avoid problems on current leakage and breakdown strength deterioration and the like, by forming a groove with sidewalls which are perpendicular to a prescribed main surface and parallel or perpendicular to an orientation flat surface and forming a semiconductor element inside this groove. CONSTITUTION:A field oxidizing film 24 is formed selectively on a surface of a P type silicon wafer 21 which has a (100) crystal face as its main surface and has an orientation flat 22 formed on this (100). A groove 23 is formed in an element region. Next, a PSG film 25 is formed and piled on the whole surface, and heat diffusion of phosphorus is performed in the silicon substrate 21 so as to form a N type impurity region 26. Successively, the PSG film 25 is peeled, and a heat oxidation film 27, polycrystalline silicon layers 28 and 29 are formed and piled thereon. The N type impurity region 26 and the polycrystalline silicon layer 28 are respectively used as electrodes so as to form a capacitive element with the heat oxidation film 27 serving as a dielectric. Since all sidewalls of the groove 23 have (100) crystal faces, the heat oxidation film 27 can be formed with a uniform thickness.

2. 发明专利

JPS62200760A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPS62200760A
公开(公告)日：1987-09-04
申请号：JP4375286
申请日：1986-02-28
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG
发明人： ASAMI TETSUYA
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108
摘要： PURPOSE:To obtain a semiconductor memory device having a large capacity and little indentation of the surface of a substrate by a method wherein a conductor having the same potential as a semiconductor substrate is formed on a gate electrode of a capacitor element with an oxide film interposed between them. CONSTITUTION:A capacitor element is so designed as to have a semiconductor substrate 11 of a first conductivity type, a groove 16 provided in the surface of this substrate 11, a semiconductor layer 17 provided inside the groove 16 and around it, a gate electrode 19 provided on this semiconductor layer 17 with a gate oxide film 18 interposed between them, and a conductor 22 which is provided on the gate electrode 19 with an oxide film 20 interposed between them and has the same potential as the substrate 11. For instance, an N layer 17 is formed inside and around the groove 16 formed in the Si substrate 11 of a P-type, a polycrystalline Si layer is formed thereon with the gate oxide film 18 interposed between them, and the gate electrode 19 is formed with resistance reduced. After a second-layer polycrystalline Si layer is deposited through the oxide film 20, subsequently, resistance is reduced and a potential take-out region 21 of an N type formed. Then, the second-layer polycrystalline Si layer is removed selectively, so as to form the conductor 22 having the same potential as the substrate 11.

3. 发明专利

JPS63161660A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63161660A
公开(公告)日：1988-07-05
申请号：JP30767786
申请日：1986-12-25
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG
发明人： ASAMI TETSUYA
IPC分类号： H01L29/78 , H01L21/8234 , H01L27/088
摘要： PURPOSE:To manufacture a semiconductor device without sacrifying characteristics of both MOSFETs, by setting widths of low-concentration impurity regions in accordance with characteristics required for respective MOS field effect transistors FETs. CONSTITUTION:MOSFETs 12 and 13 are provided with low-concentration impurity regions 125 and 135 for improving hot carrier resisting characteristics. The regions are different from each other, in widths (w) in their horizontal direction (x). For example, assuming that the MOSFETs 12 and 13 for hot carrier resistance and for high breakdown, respectively, are made and both widths (w) are made w1 and w2, respectively, a relation w1

4. 发明专利

JPS61174754A SEMICONDUCTOR PACKAGE 失效
公开(公告)号：JPS61174754A
公开(公告)日：1986-08-06
申请号：JP1628785
申请日：1985-01-30
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG
发明人： ASAMI TETSUYA
IPC分类号： H01L23/12 , H01L23/498 , H01L23/50 , H05K3/34
摘要： PURPOSE:To make it possible to perform mounting on both surface of a PC board, by making lead terminals, which are provided on the lower surface of an outer container, approximately semicircular contact terminals, which are brought into close contacted with the lower surface. CONSTITUTION:Approximately semicircular contact terminals 4 are formed on the bottom surface part of an outer container 1. By making each terminal 4 approximately semicircular, the close contact property with the contact parts on a PC board becomes good. When the terminal 4 is mounted on one surface of the PC board, the terminal 4 is not protruded to the back surface. Therefore, contact wirings can be also provided on the back surface. The contact of a package and a socket at a final test and the like can be simply performed.

5. 发明专利

JPS63299251A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63299251A
公开(公告)日：1988-12-06
申请号：JP13379787
申请日：1987-05-29
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG
发明人： KAGAMI SHOICHI , ASAMI TETSUYA
IPC分类号： H01L21/3205 , H01L21/768
摘要： PURPOSE:To prevent the characteristics and the reliability of a device from reducing even though the device is finely formed by a method wherein a contact hole is provided on a high-concentration impurity layer under a first insulating film, a flattened film on a second insulating film is removed to make the flattened film remain only in the contact hole and the contact hole is filled with the flattened film. CONSTITUTION:An element region 20 is formed on a P-type Si substrate 18 and a high-concentration impurity layer 21 is formed. Then, a CVD-SiO2 film 22 (a first insulating film) is formed by deposition on the whole surface and an anisotropic dry etching is performed to provide a contact hole 23 in the film 22. After that, a poly Si layer 24 is deposition-formed on the whole surface and As ions are implanted in this layer. Then, the layer 24 is subjected to thermal oxidation to form a thermal oxidation film 25 (a second insulating film). Subsequently, a poly Si layer 26 is deposition-formed by an LPCVD method, the surface of this layer 26 is subjected to anisotropic dry etching to remove the layer 25 which is exposed. Then, an Al layer or an Al-Si layer is formed on the whole surface by a sputtering method and a patterning is performed to form a wiring 27.

6. 发明专利

JPS63172453A MOS CAPACITOR 失效
公开(公告)号：JPS63172453A
公开(公告)日：1988-07-16
申请号：JP332087
申请日：1987-01-12
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG
发明人： ASAMI TETSUYA
IPC分类号： H01L27/04 , H01L21/822 , H01L27/10
摘要： PURPOSE:To suppress decrease in stored electric charge accompanied by high integration density, by forming an approximately semispherical groove in the surface of a semiconductor substrate, and providing an insulating film and a gate electrode along the groove. CONSTITUTION:A thermal oxide film 25 for an etching mask is formed on a silicon substrate 11. Resist 26 is patterned, and the thermal oxide film 25 is removed. Then a semispherical groove 12 is formed by etching. The entire parts of the thermal oxide film 25 and the resist 26 are removed. A gate insulating film 14 is grown on the surrounding surface of the groove 12 by thermal oxidation. An N-type impurity layer 13 is formed by ion implantation, and polycrystalline silicon is formed. Impurities are introduced in the polycrystalline silicon and the resistance value of the silicon is decreased. Thus a gate electrode 15 is formed. The manufacture of an MOS capacitor is finished by patterning. Since the surface of the capacitor has the spherical surface, the area of the capacitor, which can be provided for the same cell area, can be made large, and the decrease in stored electric charge can be suppressed.

7. 发明专利

JPS6312176A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6312176A
公开(公告)日：1988-01-19
申请号：JP15497686
申请日：1986-07-03
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG
发明人： MORITA SHIGERU , YOSHIKAWA KUNIYOSHI , KAGAMI SHOICHI , KINUGAWA MASAAKI , ASAMI TETSUYA
IPC分类号： H01L21/8247 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PURPOSE:To shorten writing time, by crossing a gate electrode and a region between a source and a drain at an acute angle in a channel region between the source and drain regions. CONSTITUTION:A channel region 12 crosses an element region 3 between a source and a drain at an acture angle. Since the channel region 12 is formed in the oblique direction, the substantiel width of the effective channel becomes wide even if the width of the element region 3 is equal. Therefore a large amount of a drain current can be made to flow. In this way, an electric field is readily concentrated between drain regions 5 and 7 and a channel region 12 in the vicinity of a field insulating film 2 in the channel region 12. This is advantageous for an EPROM, which is operated by utilizing avalanche injection. The length of the side surface of a gate electrode, which passes on the element region 3, increases in comparison with a conventional type. Therefore, a region, in which electric charge is injected, is increased, and writing characteristics are improved.

8. 发明专利

JPS634668A MOS TYPE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS634668A
公开(公告)日：1988-01-09
申请号：JP14862586
申请日：1986-06-25
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG
发明人： KAGAMI SHOICHI , MORITA SHIGERU , KINUGAWA MASAAKI , ASAMI TETSUYA
IPC分类号： H01L27/092 , H01L21/8234 , H01L21/8238 , H01L27/08 , H01L27/088 , H01L29/78
摘要： PURPOSE:To increase hot carrier resistance regarding an MOS transistor to which normal voltage is applied, and to elevate high-voltage resistance regarding an MOS transistor, to which high voltage is applied, by setting the concentration profiles of low impurity concentration regions in drain regions in two kinds or more between each MOS transistor. CONSTITUTION:Since the concentration profile of an N type region 17 (or 18) on the low concentration side of a drain region is brought to a comparatively high value in an MOS transistor formed in an element region 14 on the right side, hot carrier breakdown strength is increased so as to have hot carrier breakdown strength for years such as approximately ten years. Since the concentration profile of an N type region 19 (or 20) on the low concentration side of a drain region is brought to a comparatively low value in an MOS transistor shaped in an element region 13 on the left side, on the other hand, breakdown strength is elevated so as to resist high voltage of approximately 15V.

9. 发明专利

JP2006093289A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2006093289A
公开(公告)日：2006-04-06
申请号：JP2004274953
申请日：2004-09-22
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： ASAMI TETSUYA
IPC分类号： H01L21/3205 , H01L23/52
摘要： PROBLEM TO BE SOLVED: To realize a semiconductor device ensuring high reliability by sustaining a low impedance of interconnect lines even if a defect resulting from a dust occurs during fabrication process.
SOLUTION: The semiconductor device has: a point 15 being supplied with an electric signal or a predetermined potential; points 12a-12d for receiving an electric signal or a potential from the supply point 15; and lattice-like interconnect lines 13 and 16 formed such that a plurality of routes exist from the supply point 15 to the receiving points 12a-12d.
COPYRIGHT: (C)2006,JPO&NCIPI

10. 发明专利

JPH11260931A METHOD FOR ESTIMATING MARKET FAILURE RATE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE FOR TEST 失效
公开(公告)号：JPH11260931A
公开(公告)日：1999-09-24
申请号：JP8501298
申请日：1998-03-15
申请人： TOSHIBA MICRO ELECTRONICS , TOSHIBA CORP
发明人： HASHIMOTO TAKEHIRO , TANAKA YUTAKA , ASAMI TETSUYA , SATO YOICHI , YAMIYA NORIAKI
IPC分类号： H01L21/82 , G01R31/26 , H01L21/02 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which an optimal initial failure screening condition is set without operating the accelerated test of all items, and provide a product development and mass production method. SOLUTION: At the time of the product development and mass production of a semiconductor device, the market failure rate of each variety is individually predicted without carrying out the accelerated test of all items, and an optimal initial failure screening condition is set. At the time of the development and mass production of a few but various semiconductors, the market failure rate of each variety is individually estimated by using a semiconductor device for test without carrying out the acceleration test of all items. At first, all items to be developed and mass-produced are classified into several item groups (1). Then, a semiconductor device for test having the average number of elements, gate area, multi-layer wiring length, and number of holes of the item group is developed. The semiconductor device for test operates design based on the simplicity of the specification of the cause of failure. That is, the semiconductor device for test has main features (design rule, MOSFET structure, and wiring structure or the like) of the item for each item group, and the specification of the defective part can be easily attained by tester analysis.

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