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1. 发明专利

JPH06310528A MANUFACTURE OF MOS TYPE SEMICONDUCTOR DEVICE OF MASK LDD STRUCTURE 失效
公开(公告)号：JPH06310528A
公开(公告)日：1994-11-04
申请号：JP32753193
申请日：1993-12-24
申请人： TOSHIBA CORP , TOSHIBA MICRO ELECTRONICS
发明人： ATSUMI SHIGERU , SAITO SHINJI , TANAKA SUMIO , OTSUKA NOBUAKI , YOSHIKAWA KUNIYOSHI , KAMEI TAKASHI
IPC分类号： H01L21/336 , H01L29/78 , H01L29/784
摘要： PURPOSE:To provide a manufacturing method for a MOS type semiconductor device of mask LDD structure wherein electrical characteristic dispersion is not generated between a plurality of transistors. CONSTITUTION:A field insulation film 24 is formed on a P-type substrate 11, gate electrodes 17, 17 are formed and semiconductor regions 25, 26, 27 are formed by diffusing N-type impurities at a low concentration into the substrate 11 by using the field insulation film 24 and the gate electrodes 17, 17 as a mask. Photoresist films 28, 28 are selectively made to remain to cover a part of the semiconductor region 25 at the side of the gate electrode 17 and a part of the semiconductor region 27 at the side of the gate electrode 17, and N-type impurities are diffused into the substrate 11 at a high concentration to form high concentration drain regions 12, 14 inside the semiconductor region 25 and inside the semiconductor region 27. The semiconductor region 25 and the semiconductor region 27 which are covered with the photoresist films 28, 28 are made to remain as low concentration drain regions 18, 19.

2. 发明专利

JPH0346196A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH0346196A
公开(公告)日：1991-02-27
申请号：JP18140989
申请日：1989-07-13
申请人： TOSHIBA CORP , TOSHIBA MICRO ELECTRONICS
发明人： SUZUKI NORIAKI , MIYAMOTO JUNICHI , OTSUKA NOBUAKI
IPC分类号： G11C17/00 , G06F11/00 , G11C16/06 , G11C16/28 , G11C29/00 , G11C29/04
摘要： PURPOSE:To prevent erroneous discrimination of read data regardless of the variance of the supply voltage to improve the reliability of a device by adding dummy capacity cells on a redundant bit line. CONSTITUTION:Plural dummy capacity cells DC are connected to a redundant bit line RBL so that the additional capacity of the line RBL is approximately equal to that of a dummy bit line DBL. If a sent column address indicates the address of memory cell array including a defective cell, a redundant cell selecting circuit 32 is operated to send the operation stop command signal of a column selector CS and sends the select signal of a redundant cell array, which is selected in stead of the memory cell array including the defective cell, to a column selector CSR. Thus, this redundant cell array is selected by the selector CSR.

3. 发明专利

JPH02187996A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH02187996A
公开(公告)日：1990-07-24
申请号：JP743489
申请日：1989-01-13
申请人： TOSHIBA CORP , TOSHIBA MICRO ELECTRONICS
发明人： IYAMA YUMIKO , MIYAMOTO JUNICHI , OTSUKA NOBUAKI , TANAKA SUMIO
IPC分类号： G11C17/00 , G11C16/06 , G11C16/28
摘要： PURPOSE:To contrive the improvement of reliability by comparing the read-out potential from a memory cell with the reference potential by a sense amplifier and executing a sense of data. CONSTITUTION:A CMOS gate circuit 49 consisting of P channel MOS transistors TR 47, 48 is provided, a gate of the TR 47 and a gate of the TR 48 are connected to a node 44 and an output node of an inverter 42, respectively, an enhancement P channel MOS TR 50 is inserted between the node 44 and a power supply voltage SW, and its gate to an output node of the gate circuit 49. When a write control signal WE is '0', and an output of the inverter 42 is '0', the power supply voltage SW is outputted from the circuit 49. Subsequently, the P channel TR 50 is turned off and a current of a path extending from the voltage SW to a ground voltage Vss comes not to flow, and it becomes '1' when the signal WE is '1' and the TR 48 in the circuit 49 is turned on, and the voltage Vss is outputted from the circuit 49. In such a way, characteristics of a dummy cell and a memory cell can be allowed to correspond with each other and high reliability is obtained.

4. 发明专利

JP2009048671A Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：JP2009048671A
公开(公告)日：2009-03-05
申请号：JP2007210885
申请日：2007-08-13
申请人： Toshiba Corp , 株式会社東芝
发明人： OTSUKA NOBUAKI
IPC分类号： G11C11/413 , G11C11/412
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device which improves both write characteristics and tolerance against disturb caused by variations of threshold voltage or the like and reduction of voltage, and suppresses increase in area, increase in power and deterioration of speed property. SOLUTION: The semiconductor storage device is provided with: a memory cell containing a first inverter IV1 to which an input end and output end are connected to cross respectively and a second inverter IV2; a reference supply wiring VSSCL which supplies reference voltage VSSC to the first inverter IV1; a reference supply wiring VSSCR which supplies reference voltage VSSC to the second inverter IV2; bit lines BL and /BL connected to the memory cell; and transfer gates TL1 and TL2 and transfer gates TR1 and TR2 which control impedance in the reference supply wirings VSSCL and VSSCR according to voltages of bit lines BL and /BL respectively. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供一种半导体存储装置，其提高写入特性和由阈值电压等的变化引起的干扰和电压的降低，并且抑制面积的增加，功率的增加和速度的劣化属性。解决方案：半导体存储装置设置有：存储单元，其包含第一反相器IV1，输入端和输出端分别连接到第一反相器IV1和第二反相器IV2; 将参考电压VSSC提供给第一反相器IV1的参考电源线VSSCL; 向第二反相器IV2供给基准电压VSSC的基准电源配线VSSCR; 连接到存储单元的位线BL和/ BL; 以及分别根据位线BL和/ BL的电压来控制参考电源配线VSSCL和VSSCR中的阻抗的传输门TL1和TL2以及传输门TR1和TR2。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2008146734A Semiconductor memory 审中-公开
标题翻译：半导体存储器
公开(公告)号：JP2008146734A
公开(公告)日：2008-06-26
申请号：JP2006331992
申请日：2006-12-08
申请人： Toshiba Corp , 株式会社東芝
发明人： FUKANO TAKESHI , YABE TOMOAKI , OTSUKA NOBUAKI
IPC分类号： G11C11/41
CPC分类号： G11C7/18
摘要： PROBLEM TO BE SOLVED: To increase the operation speed of a semiconductor memory.
SOLUTION: This semiconductor memory has sub-arrays connecting the memory cells arranged in matrixes, local bit lines connected to memory cells arranged in the column direction in the sub-arrays, global bit lines connected to the local bit lines, and a column decoder connected to the global bit lines. However, in the farthest sub-array formed in an area most apart from the column decoder among those sub-arrays, the global bit lines are not formed.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提高半导体存储器的操作速度。解决方案：该半导体存储器具有连接以矩阵排列的存储单元的子阵列，连接到子阵列中的列方向上布置的存储单元的本地位线，连接到局部位线的全局位线，以及列解码器连接到全局位线。然而，在这些子阵列中与列解码器最远的区域中形成的最远的子阵列中，不形成全局位线。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2001094048A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001094048A
公开(公告)日：2001-04-06
申请号：JP26952099
申请日：1999-09-22
申请人： TOSHIBA CORP
发明人： OTSUKA NOBUAKI , KAMEDA YASUSHI
IPC分类号： H01L27/04 , G11C7/10 , G11C11/40 , H01L21/822 , H03K19/0175
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having an output impedance control circuit for performing highly accurate impedance adjustment for an output buffer circuit, even if power supply voltage is reduced in a semiconductor device having programmable impedance control function. SOLUTION: The gate terminal level of a first load transistor connected to an external resistor, whose impedance is specified is controlled, so that the voltage of the connection node becomes 1/2 the drive power supply voltage of an output buffer circuit. A second load transistor, that is the same conductor as the first load transistor and whose gate, is commonly connected to the first load transistor, and a dummy output buffer circuit that is used for impedance matching are connected in series, and the size of the dummy buffer circuit is controlled so that the drain voltage of a group of transistors of the dummy buffer circuit becomes 1/2 the drive power supply voltage of the output buffer circuit.

7. 发明专利

JP2001093297A TEST DEVICE FOR SEMICONDUCTOR 失效
公开(公告)号：JP2001093297A
公开(公告)日：2001-04-06
申请号：JP26992199
申请日：1999-09-24
申请人： TOSHIBA CORP
发明人： OTSUKA NOBUAKI
IPC分类号： G11C11/413 , G06F12/16 , G11C29/00 , G11C29/06
摘要： PROBLEM TO BE SOLVED: To suppress a peak current generated by batch selection of word lines, non-selection control, setting of a write-in level of a bit line, and batch control of recovery, when accelerated stress is applied to a memory cell in burn-in and the like and screening is performed. SOLUTION: This device is provided with a cell 11 connected to word lines WL and a pair of bit line BL, /BL, a transistor 13 conducted in a normal operation state and charging a pair of bit line, a test mode setting means setting a test mode, a control means controlling so that the transistor 13 becomes in a non-conduction state at the time of a test mode, a dummy word line DWL brought into a selection state at the time of a test mode, and a dummy cell 16 connected to a dummy word line and a pair of bit line and having same constitution as the cell 11.

8. 发明专利

JP2000163994A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JP2000163994A
公开(公告)日：2000-06-16
申请号：JP33306298
申请日：1998-11-24
申请人： TOSHIBA CORP
发明人： OTSUKA NOBUAKI
IPC分类号： G11C11/413 , G01R31/28 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/50 , G11C29/56
摘要： PROBLEM TO BE SOLVED: To shorten the test time of the setup time and hold time of input data and to improve the reliability of a test. SOLUTION: Address data are inputted to an address register 13 through a pad 11 and an input buffer 12 and used to read and write a memory core 22. When a setup and a hold time are tested, a control circuit 5 switches a multiplexer 31 to a pass side, the output side of the address register 13 and the output register 32 are connected, and the address data held in the address register 13 are transferred directly to an output register 32. Consequently, the address data of the output register 32 are read out to an external tester, etc., through an input/output pad, and it can be checked whether or not the input address data themselves are correct. Since the input address is checked directly, test can be conducted in a short time with high reliability.

9. 发明专利

JP2000101414A SEMICONDUCTOR INPUT CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JP2000101414A
公开(公告)日：2000-04-07
申请号：JP27218698
申请日：1998-09-25
申请人： TOSHIBA CORP
发明人： OTSUKA NOBUAKI , HIRABAYASHI OSAMU
IPC分类号： H01L21/8238 , G01R31/28 , G11C11/401 , G11C11/409 , G11C29/00 , G11C29/12 , H01L27/092 , H03K19/00 , H03K19/0175
摘要： PROBLEM TO BE SOLVED: To obtain a semiconductor input circuit where a through-current is eliminated, while properly reflecting a logic level of an external input signal onto the inside of the circuit in a test mode. SOLUTION: This semiconductor input circuit is provided with a differential amplifier circuit which has a current mirror circuit consisting of 1st conduction type 1st and 2nd MOS transistors(TRs) 11, 12, whose gates respectively receive an external input signal and a reference level signal and whose sources are connected in common and of 2nduction type two MOS TRs 21, 22 whose drains are connected respectively to drains of the 1st and 2nd MOS TRs 11, 12. In this case, a transfer gate 30 that is on/off-controlled by a test use control signal is connected between the gate node of the current mirror circuit and an external input node, to which the external input signal is applied.

10. 发明专利

JPH10125100A NONVOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH10125100A
公开(公告)日：1998-05-15
申请号：JP27801696
申请日：1996-10-21
申请人： TOSHIBA CORP
发明人： MIYAGAWA TADASHI , OTSUKA NOBUAKI
IPC分类号： G01R31/28 , G06F12/14 , G06F21/02 , G11C16/02 , G11C16/22 , G11C29/12 , G11C29/52 , G11C29/00
摘要： PROBLEM TO BE SOLVED: To inspect presence or absence of protection setting without writing or erasing operation. SOLUTION: Erasing circuits 12 are provided correspondingly to bocks BLK(0) to BLK(n) of a memory cell array 11. A protection circuit 23 outputs protect signals PROT0 to PROTn each representing presence or absence of protection setting for data of the cell. In a test mode, an inspecting means in the circuit 12 detects the presence or absence of the protection setting based on the signals PROT0 to PROTn, and alters the voltage to be applied to a source of the cell of each block in response to the presence or absence of the protection setting. As a result, when a normal reading operation is conducted, the data to be read are different in the protection setting block and unsetting block.

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