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1. 发明专利

JP2002141366A METHOD FOR MOUNTING CONDUCTIVE BALL 失效
公开(公告)号：JP2002141366A
公开(公告)日：2002-05-17
申请号：JP2000335519
申请日：2000-11-02
申请人： TOSHIBA CORP
发明人： TOMONO AKIRA , KAWAI KAORU , YAMAMOTO TETSUYA
IPC分类号： H05K3/34 , H01L21/60
摘要： PROBLEM TO BE SOLVED: To provide a means for aligning conductive balls in a prescribed array on a ball grid array base plate or the like. SOLUTION: A method for mounting the conductive ball comprises a first step of displacing and superposing perforated parts of an aligning mask 21 and a supply mask 21 having substantially the same arrays and same opening shapes, a second step of introducing the balls 1 into holes 23 of the aligning mask, and a third step of bringing the opening parts 23 and 24 of the masks 21 and 22 into coincidence and disposing the balls 1 in the prescribed array on the base plate.

2. 发明专利

JP2012195388A Semiconductor device manufacturing method and semiconductor device 审中-公开
标题翻译：半导体器件制造方法和半导体器件
公开(公告)号：JP2012195388A
公开(公告)日：2012-10-11
申请号：JP2011057233
申请日：2011-03-15
申请人： Toshiba Corp , 株式会社東芝
发明人： TOMONO AKIRA , KUROSAWA TETSUYA , FUJITA TSUTOMU , KIRITANI MIYOSHI , TAKU SHINYA
IPC分类号： H01L21/301
CPC分类号： H01L23/3114 , H01L21/561 , H01L21/568 , H01L21/6836 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To cut an adhesive layer formed on a semiconductor wafer without applying a load and the like that causes partial disconnection of a wiring portion of a semiconductor element, contamination by cutting debris, and chip cracks.SOLUTION: According to an embodiment, a semiconductor device manufacturing method comprises: a step of forming cutting trenches 31 on an element formation surface of a semiconductor wafer 10 for sectioning the element formation surface into a plurality of regions; a step of arranging resin 32 in the cutting trenches 31; a step of affixing a protective tape 33 on the element formation surface of the semiconductor wafer 10; a step of grinding a rear face of the semiconductor wafer 10 until reaching the cutting trenches 31 for thinning the semiconductor wafer 10; a step of forming an adhesive layer 35 on the rear face of the semiconductor wafer 10; a step of peeling the protective tape 33; and a step of cutting the adhesive layer 35 together with the resin 32 along the cutting trenches 31 to divide the semiconductor wafer 10 into a plurality of semiconductor chips 1. The resin 32 is partially arranged in the cutting trenches 31 such that mutual movement of neighboring regions is regulated.
摘要翻译：要解决的问题：为了切割形成在半导体晶片上的粘合层，而不施加导致半导体元件的布线部分的部分断开的负载等，被切割碎屑的污染和芯片裂纹。解决方案：根据实施例，半导体器件制造方法包括：在半导体晶片10的元件形成表面上形成切割沟槽31以将元件形成表面分割成多个区域的步骤; 在切割槽31中设置树脂32的步骤; 将保护带33固定在半导体晶片10的元件形成表面上的步骤; 研磨半导体晶片10的后表面直到达到用于使半导体晶片10变薄的切割沟槽31的步骤; 在半导体晶片10的背面上形成粘接层35的工序; 剥离保护带33的步骤; 以及沿着切割沟槽31与树脂32一起切割粘合剂层35以将半导体晶片10分成多个半导体芯片1的步骤。树脂32部分地布置在切割槽31中，使得相邻的地区受到监管。版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2012164953A Semiconductor device and method and apparatus of manufacturing the same 有权
标题翻译：半导体器件及其制造方法和装置
公开(公告)号：JP2012164953A
公开(公告)日：2012-08-30
申请号：JP2011160586
申请日：2011-07-22
申请人： Toshiba Corp , 株式会社東芝
发明人： KUROSAWA TETSUYA , TAKU SHINYA , TOMONO AKIRA
IPC分类号： H01L21/301 , H01L21/304
CPC分类号： H01L21/78 , H01L21/6836
摘要： PROBLEM TO BE SOLVED: To cut an adhesive layer formed on a semiconductor wafer without partially cutting a wiring part of a semiconductor element, soiling the semiconductor element with cutting scraps, or putting a load causing chip fractures.SOLUTION: According to an embodiment, there are provided steps of: forming a cutting groove 31 on an element formation surface of a semiconductor wafer 1', on which a semiconductor element is formed; attaching a protective tape 32 on the element formation surface of the semiconductor wafer 1'; reducing a thickness of the semiconductor wafer 1' by griding a back surface of the semiconductor wafer 1' and dividing the semiconductor wafer 1' into a plurality of semiconductor chips 1; forming an adhesive layer 33 on the back surface of the semiconductor wafer 1'; cutting the adhesive layer 33 so as to separate the adhesive layer 33 according to each of the semiconductor chips 1; and peeling off the protective tape 32. The step of cutting the adhesive layer 33 so as to separate the adhesive layer 33 according to each of the semiconductor chips 1 is performed by spraying a high-pressure air on the adhesive layer 33 while heating the adhesive layer 33 formed on the back surface of the semiconductor wafer 1' so as to let the adhesive layer 33 melt or soften.
摘要翻译：要解决的问题：为了切割形成在半导体晶片上的粘合剂层，而不会部分地切割半导体元件的布线部分，用切割屑污染半导体元件，或者引起引起芯片断裂的负载。解决方案：根据一个实施例，提供了以下步骤：在半导体晶片1'的元件形成表面上形成切割槽31，在其上形成半导体元件; 在半导体晶片1'的元件形成表面上附着保护带32; 通过磨削半导体晶片1'的背面并将半导体晶片1'分割成多个半导体芯片1来减小半导体晶片1'的厚度; 在半导体晶片1'的背面上形成粘合剂层33; 切割粘合剂层33以分离根据每个半导体芯片1的粘合剂层33; 并剥离保护带32.根据每个半导体芯片1切割粘合剂层33以分离粘合剂层33的步骤通过在粘合剂层33上喷涂高压空气同时加热粘合剂形成在半导体晶片1'的背面上的层33，以使粘合剂层33熔融或软化。版权所有（C）2012，JPO＆INPIT

4. 发明专利

JP2006054360A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006054360A
公开(公告)日：2006-02-23
申请号：JP2004235850
申请日：2004-08-13
申请人： Toshiba Corp , 株式会社東芝
发明人： TOMONO AKIRA
IPC分类号： H01L21/60
CPC分类号： H01L24/16 , H01L21/563 , H01L24/03 , H01L24/05 , H01L24/29 , H01L24/83 , H01L2224/0401 , H01L2224/05624 , H01L2224/05647 , H01L2224/13099 , H01L2224/131 , H01L2224/16225 , H01L2224/29109 , H01L2224/29111 , H01L2224/2919 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/75252 , H01L2224/75743 , H01L2224/83192 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01078 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/0133 , H01L2924/014 , H01L2924/05042 , H01L2924/09701 , H01L2924/30105 , H01L2924/3511 , H05K3/3436 , H05K3/3463 , H05K2201/10977 , H05K2201/10992 , Y02P70/613 , H01L2924/00014 , H01L2924/01039 , H01L2924/00 , H01L2924/01083 , H01L2224/13111 , H01L2924/3512 , H01L2924/0665
摘要： PROBLEM TO BE SOLVED: To prevent disconnection of a bump connection part due to retroflexion of a circuit board, in a semiconductor device in which flip chip connection is made by using a sealing resin having a flux function.
SOLUTION: A semiconductor element 11 comprises a solder bump 15 formed on a first electrode pad 12 through a first low-temperature soldering layer 16. A circuit board 13 comprises a second electrode pad 14 corresponding to the first electrode pad 12, and a second low-temperature soldering layer 17 is formed on the second electrode pad 14. These semiconductor element 11 and circuit board 13 are flip-chip-connected together by using the sealing resin 18 having the flux function.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了防止由于电路板的反向而导致的凸块连接部分的断开，在通过使用具有磁通功能的密封树脂制成倒装芯片连接的半导体器件中。解决方案：半导体元件11包括通过第一低温焊接层16形成在第一电极焊盘12上的焊料凸块15.电路板13包括对应于第一电极焊盘12的第二电极焊盘14，以及在第二电极焊盘14上形成第二低温焊接层17.这些半导体元件11和电路板13通过使用具有助焊功能的密封树脂18倒装连接在一起。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2007149846A Manufacturing method for semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2007149846A
公开(公告)日：2007-06-14
申请号：JP2005340392
申请日：2005-11-25
申请人： Toshiba Corp , Toshiba Lsi Package Solutions Corp , 東芝Lsiパッケージソリューション株式会社 , 株式会社東芝
发明人： SUGIZAKI YOSHIAKI , NOMURA HIROSHI , KOMUDA NAOYUKI , HONMA SOICHI , TOMONO AKIRA
IPC分类号： H01L21/60
CPC分类号： H01L24/81 , H01L2224/16225 , H01L2224/81193 , H01L2924/00011 , H01L2924/01322 , H01L2224/81805
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device which reduces the possibility of the occurrence of melting connection failures, as compared to conventional cases and can improve the reliability and productivity. SOLUTION: According to the manufacturing method for the semiconductor device, a first connection terminal is connected to a second connection terminal by a heating process, where a solder bump is melted by exposing it to a temperature higher than the melting point of the solder bump; and during the heating process, the solder bump is exposed at least twice or more times, to a temperature higher than the melting point of the solder bump, and is cooled at least twice or more times to a temperature lower than the melting point of the solder bump. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：与常规情况相比，提供一种减少熔融连接故障发生的可能性的半导体器件的制造方法，并且可以提高可靠性和生产率。解决方案：根据半导体器件的制造方法，第一连接端子通过加热工艺连接到第二连接端子，其中通过将焊料凸点暴露于高于熔点焊锡凸块并且在加热过程中，焊料凸块暴露至少两次或更多次，达到高于焊料凸点的熔点的温度，并且被冷却至少两倍或更多倍于低于焊锡凸块版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2005011838A Semiconductor device and its assembling method 审中-公开
标题翻译：半导体器件及其组装方法
公开(公告)号：JP2005011838A
公开(公告)日：2005-01-13
申请号：JP2003170905
申请日：2003-06-16
申请人： Toshiba Corp , 株式会社東芝
发明人： TOMONO AKIRA , HONMA SOICHI
IPC分类号： H01L21/56 , H01L21/60 , H01L23/31 , H01L23/485 , H01L23/498
CPC分类号： H01L24/12 , H01L21/563 , H01L23/3128 , H01L23/49811 , H01L24/11 , H01L24/16 , H01L24/29 , H01L24/81 , H01L24/83 , H01L2224/05001 , H01L2224/05022 , H01L2224/05026 , H01L2224/05027 , H01L2224/0508 , H01L2224/05572 , H01L2224/1147 , H01L2224/13099 , H01L2224/13111 , H01L2224/16225 , H01L2224/29109 , H01L2224/29111 , H01L2224/2919 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/81801 , H01L2224/83192 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01056 , H01L2924/01067 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/0133 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/1579 , H01L2924/19043 , H01L2924/30105 , H01L2924/351 , H01L2924/01014 , H01L2924/01083 , H01L2924/00 , H01L2924/00014 , H01L2224/13109 , H01L2924/3512 , H01L2924/00012 , H01L2224/05664 , H01L2224/05155 , H01L2224/05166
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that can prevent the breakage of the surface of a semiconductor chip element, especially, the breakage of a low-dielectric constant insulating film disposed immediately above the solder used for connecting a semiconductor chip and a substrate to each other without generating voids in a sealing resin, by minimizing a thermal stress caused by the reflow soldering of the solder; and to provide a method of assembling the device.
SOLUTION: The semiconductor device is provided with a chip mounting substrate 1 having a first and a second principal surfaces facing each other, a plurality of substrate-side internal electrode pads 2 disposed on the second principal surface, first solder balls 3 connected to the electrode pads 2. The device is also provided with second solder balls 4 connected to the first solder balls 3 and having high melting points, the semiconductor chip 6 connected to the second solder balls 4, and the sealing resin 7 encapsulated in the peripheries of the first and the second solder balls 3 and 4.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够防止半导体芯片元件的表面破损的半导体器件，特别是设置在用于连接半导体芯片的焊料正上方的低介电常数绝缘膜的断裂并且通过使由焊料的回流焊接引起的热应力最小化，在密封树脂中不产生空隙而彼此相对的基板; 并提供组装该装置的方法。解决方案：半导体器件设置有具有彼此面对的第一和第二主表面的芯片安装基板1，设置在第二主表面上的多个基板侧内部电极焊盘2，第一焊球3连接该装置还设置有连接到第一焊球3并具有高熔点的第二焊球4，连接到第二焊球4的半导体芯片6和封装在周边中的密封树脂7 的第一和第二焊球3和4.版权所有（C）2005，JPO＆NCIPI

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