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1. 发明专利

JP2013197209A Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013197209A
公开(公告)日：2013-09-30
申请号：JP2012061142
申请日：2012-03-16
申请人： Toshiba Corp , 株式会社東芝
发明人： FUJITA TSUTOMU , TAKANO YUSUKE , KAWATO MASATOSHI
IPC分类号： H01L23/28 , H01L23/00
CPC分类号： H01L24/97 , H01L24/73 , H01L2224/04042 , H01L2224/32225 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2224/97 , H01L2924/1531 , H01L2924/181 , H01L2924/3025 , H01L2924/00012 , H01L2224/85 , H01L2224/83 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a method for manufacturing the same, capable of easily making a shield layer and a substrate GND conductive, improving a shield effect, and reducing a manufacturing cost.SOLUTION: A method for manufacturing a semiconductor device includes the steps of: mounting a plurality of semiconductor chips 20 on a substrate 10 and forming a conductor 30 whose upper surface is higher than a surface of the substrate along a peripheral part of the chip including a dicing line; coating each semiconductor chip 20 and the conductor 30 with a resin layer 40; cutting the resin layer 40 by half along the dicing line and exposing an upper surface of the conductor 30; coating the conductor 30 exposed due to the half cutting and the resin layer 40 with a conductive material; and cutting the substrate 10, the conductor 30, and the conductive material 40 on the dicing line into individual devices.
摘要翻译：要解决的问题：为了提供能够容易地使屏蔽层和基板GND导电，提高屏蔽效果并降低制造成本的半导体装置及其制造方法。解决方案：半导体制造方法装置包括以下步骤：将多个半导体芯片20安装在基板10上，并沿着包括切割线的芯片的周边部分形成上表面高于基板表面的导体30; 用树脂层40涂覆每个半导体芯片20和导体30; 沿着切割线将树脂层40切割一半并暴露导体30的上表面; 用导电材料涂覆由于半切割而露出的导体30和树脂层40; 并将切割线上的基板10，导体30和导电材料40切割成单独的装置。

2. 发明专利

JP2013012690A Processing method and processing device of semiconductor wafer, and semiconductor wafer 审中-公开
标题翻译：半导体滤波器和半导体滤波器的处理方法和处理器件
公开(公告)号：JP2013012690A
公开(公告)日：2013-01-17
申请号：JP2011146049
申请日：2011-06-30
申请人： Toshiba Corp , 株式会社東芝
发明人： TAKU SHINYA , SHIMIZU NORIKO , FUJITA TSUTOMU
IPC分类号： H01L21/304 , B24B1/00
CPC分类号： H01L21/304 , B24B7/228 , H01L21/3043
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor wafer which is unlikely to cause cracks though a thickness is reduced, and provide a processing method and a processing device of the semiconductor wafer.SOLUTION: According to an embodiment, a semiconductor wafer processing method comprises: a process of grinding with a first grindstone 22, an outer periphery of a rear face of a semiconductor wafer 10 on which a semiconductor element is formed on a surface to form an annular groove 12; a process of grinding a salient 14 on the inner side of the groove 12 by a second grindstone 24a to form a recess 20 integral with the groove 12 on the rear face of the semiconductor wafer 10; and a process of further grinding with a third grindstone 26a, a bottom face of the recess 20 including a ground surface by the second grindstone 24a.
摘要翻译：要解决的问题：提供一种半导体晶片，其提供了半导体晶片的处理方法和处理装置，该半导体晶片通过减小厚度而不会产生裂纹。解决方案：根据实施例，半导体晶片处理方法包括：利用第一砂轮22，半导体晶片10的背面的外周在其上形成有半导体元件的表面上研磨的工艺，形成环形槽12; 通过第二砂轮24a在槽12的内侧研磨突出部14的工序，与半导体晶片10的背面上的槽12形成一体的凹部20; 以及通过第三砂轮26a进一步磨削的过程，凹部20的底面由第二砂轮24a包括地面。版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2015053419A 半導体装置の製造方法及び半導体製造装置有权
标题翻译：制造半导体器件的方法和半导体制造装置
公开(公告)号：JP2015053419A
公开(公告)日：2015-03-19
申请号：JP2013186101
申请日：2013-09-09
申请人：株式会社東芝 , Toshiba Corp
发明人： FUJITA TSUTOMU , SUGISAWA YOSHIFUMI
IPC分类号： H01L21/683 , H01L21/301
摘要：【課題】半導体チップへのダメージを抑制しつつ、半導体ウェーハ及び粘着層の少なくとも一方を確実に分割できる半導体製造装置を提供する。【解決手段】実施形態の半導体製造装置は、半導体ウェーハが貼り付けられたテープの前記半導体ウェーハの周囲に位置する余白部分に貼り付けられたリングを保持する保持機構と、リングに対して相対的に上昇することにより前記テープを拡張するステージとを具備する。ステージは半導体ウェーハの外周領域を除く中央領域を吸着する第1の吸着部を有する。【選択図】図1
摘要翻译：要解决的问题：提供一种半导体制造装置，其可以可靠地划分半导体晶片和粘合剂层中的至少一个，同时抑制对半导体芯片的损害。解决方案：根据实施例的半导体制造装置包括：保持结构，粘附在半导体晶片周围的位于半导体晶片周围的边缘的环; 以及相对于环相对上升并从而使带膨胀的台。该台具有用于吸附不包括半导体晶片的外围区域的中心区域的第一吸入部。

4. 发明专利

JP2012195388A Semiconductor device manufacturing method and semiconductor device 审中-公开
标题翻译：半导体器件制造方法和半导体器件
公开(公告)号：JP2012195388A
公开(公告)日：2012-10-11
申请号：JP2011057233
申请日：2011-03-15
申请人： Toshiba Corp , 株式会社東芝
发明人： TOMONO AKIRA , KUROSAWA TETSUYA , FUJITA TSUTOMU , KIRITANI MIYOSHI , TAKU SHINYA
IPC分类号： H01L21/301
CPC分类号： H01L23/3114 , H01L21/561 , H01L21/568 , H01L21/6836 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To cut an adhesive layer formed on a semiconductor wafer without applying a load and the like that causes partial disconnection of a wiring portion of a semiconductor element, contamination by cutting debris, and chip cracks.SOLUTION: According to an embodiment, a semiconductor device manufacturing method comprises: a step of forming cutting trenches 31 on an element formation surface of a semiconductor wafer 10 for sectioning the element formation surface into a plurality of regions; a step of arranging resin 32 in the cutting trenches 31; a step of affixing a protective tape 33 on the element formation surface of the semiconductor wafer 10; a step of grinding a rear face of the semiconductor wafer 10 until reaching the cutting trenches 31 for thinning the semiconductor wafer 10; a step of forming an adhesive layer 35 on the rear face of the semiconductor wafer 10; a step of peeling the protective tape 33; and a step of cutting the adhesive layer 35 together with the resin 32 along the cutting trenches 31 to divide the semiconductor wafer 10 into a plurality of semiconductor chips 1. The resin 32 is partially arranged in the cutting trenches 31 such that mutual movement of neighboring regions is regulated.
摘要翻译：要解决的问题：为了切割形成在半导体晶片上的粘合层，而不施加导致半导体元件的布线部分的部分断开的负载等，被切割碎屑的污染和芯片裂纹。解决方案：根据实施例，半导体器件制造方法包括：在半导体晶片10的元件形成表面上形成切割沟槽31以将元件形成表面分割成多个区域的步骤; 在切割槽31中设置树脂32的步骤; 将保护带33固定在半导体晶片10的元件形成表面上的步骤; 研磨半导体晶片10的后表面直到达到用于使半导体晶片10变薄的切割沟槽31的步骤; 在半导体晶片10的背面上形成粘接层35的工序; 剥离保护带33的步骤; 以及沿着切割沟槽31与树脂32一起切割粘合剂层35以将半导体晶片10分成多个半导体芯片1的步骤。树脂32部分地布置在切割槽31中，使得相邻的地区受到监管。版权所有（C）2013，JPO＆INPIT

5. 发明专利

JPS61294526A AUTOMATIC CONTROL METHOD FOR CAPACITOR 失效
公开(公告)号：JPS61294526A
公开(公告)日：1986-12-25
申请号：JP13607485
申请日：1985-06-24
申请人： TOSHIBA CORP
发明人： FUJITA TSUTOMU
IPC分类号： G05F1/70 , H02J3/18
摘要： PURPOSE:To prevent a hunting phenomenon of control by performing the automatic control of a capacitor after deciding whether or not the estimated reactive power and the estimated power factor set after control are kept under a set level only when said reactive power and power factor are different from the present polarity. CONSTITUTION:A phase advance capacitor 17 which improves the power factor of a power system is connected to the power system via a switch 18 which is controlled by a control computer 11. The computer 11 is provided with a central processor CPU12 for various arithmetic processes and a process input/ output device PI/O13. Then the power and the reactive power of the power system are supplied by a power converter 15 and a reactive power converter 16 via the PI/O13. Then the reactive power and the power factor of the power system are compared with the set values at the phase delay and advance sides respectively. It is decided whether or not said reactive power and power factor are kept under a set level only when these reactive power and power factor are different from the present polarity. Thus the capacitor 17 is controlled automatically.

6. 发明专利

JPH04364694A CONTROL SYSTEM 失效
公开(公告)号：JPH04364694A
公开(公告)日：1992-12-17
申请号：JP13994691
申请日：1991-06-12
申请人： TOSHIBA CORP
发明人： FUJITA TSUTOMU
IPC分类号： H04Q9/00
摘要： PURPOSE:To prevent a control object device from being subjected to mis-control even when noise invades in a transmission line or the like. CONSTITUTION:When a control request signal sent from a central controller 1 is received by a site controller 5, the site controller 5 generates a confirmation request signal corresponding to the control request signal and returns the signal to the central controller 1. When the confirmation request signal corresponds to the control request signal, it is discriminated that a correct control request signal is sent to the site controller 5, a control enable signal is sent from the central controller 1 to allow the site controller 5 to implement the control of a control object device corresponding to the control request signal.

7. 发明专利

JPH04159896A CONTROL SYSTEM 失效
公开(公告)号：JPH04159896A
公开(公告)日：1992-06-03
申请号：JP28431590
申请日：1990-10-24
申请人： TOSHIBA CORP
发明人： FUJITA TSUTOMU
IPC分类号： G08B29/16 , G08B23/00 , H04Q9/00
摘要： PURPOSE:To prevent the occurrence of erroneous control of equipment to be controlled caused by noise by reproducing a control request signal based on one control data for controlling the equipment to be controlled when the data obtained by inverting selective control data supplied through a scan transmitter coincide with the selected control data. CONSTITUTION:A transmission-side controller 1 generates selected control data of plural bits corresponding to a control request signal and inverted selected control data obtained by inverting the selected control data and both control data are transmitted to a reception-side controller 5 through a scan transmitter 2. When the controller 5 discriminates that the selected control data and inverted selected control data transmitted through the transmitter 2 coincide with each other, the controller 5 reproduces the control request signal on the basis of the inverted selected or selected control data and controls equipment to be controlled. Therefore, even when noise gets into a transmission line, erroneous control of the equipment to be controlled can be prevented.

8. 发明专利

JPH02127856A KEY MANAGEMENT DEVICE 失效
公开(公告)号：JPH02127856A
公开(公告)日：1990-05-16
申请号：JP28028488
申请日：1988-11-08
申请人： TOSHIBA CORP
发明人： FUJITA TSUTOMU
IPC分类号： H04M3/42 , E05B49/00 , G06F13/00 , G06Q50/00 , G06Q50/16 , H04M11/00
摘要： PURPOSE:To operate an electronic mail device automatically in interlocking with the key management operation by connecting the key management device and the electronic mail device via a transmission line, outputting the corresponding electronic mail automatically in interlocking with the extraction of a key and outputting a power interruption command of the corresponding electronic mail device in interlocking with the return of the key. CONSTITUTION:When a magnetic card carried by a tenant resident is inserted to a card reader 2, a password is collated, a correspondent mail box 1 is unlocked in the case of coincidence to attain the extraction and return of the key. When the tenant resident extracts the key from the mail box 1, a power application command is outputted to the correspondent electronic mail device 5 in interlocking with the extraction and an electronic mail is outputted automatically. When the key is returned in the mail box, a power interruption command of the correspondent electronic mail device 5 is outputted in interlocking therewith. Thus, power application to the electronic mail box, mail output and power interruption in interlocking with the extraction/return of the key from/to the mail box are implemented automatically timely without manual intervention.

9. 发明专利

JPS61208516A SUPERVISORY UNIT 失效
公开(公告)号：JPS61208516A
公开(公告)日：1986-09-16
申请号：JP4826385
申请日：1985-03-13
申请人： TOSHIBA CORP
发明人： FUJITA TSUTOMU
IPC分类号： H02J13/00 , G05B23/02
摘要： PURPOSE:To analyze a fault at accident effectively by storing the data at acci dent and delivering a series of data stored by a tracing request of an operator to a printer and a monitor panel at the same interval as that of the accident mode. CONSTITUTION:A control computer 10 consists of a central arithmetic unit CPU 11, a process input/output device 12 and a main memory 13. The information given from a process 14 is supplied via the device 12 to undergo the arithmetic processing through the CPU 11 and stored in the memory 13. A monitor panel 15 serving as a display device displays the state of each device, and these states are recorded by a printer 16. When the process 14 has a fault, etc., the CPU 11 decides a state change or a fault of a device. If a fault is decided, the analog quantity of the process 14 is calculated immediately after occurrence of the fault together with the time passed after occurrence of the fault. These calculated analog quantity and time are stored in the memory 13. If an operator requests the regeneration of the accident through an operating panel 17, said stored analog quantity is displayed successively in the same time chart as that used in the fault generation mode.

10. 发明专利

JPH03139701A CONTROL SYSTEM 失效
公开(公告)号：JPH03139701A
公开(公告)日：1991-06-13
申请号：JP27818189
申请日：1989-10-25
申请人： TOSHIBA CORP
发明人： FUJITA TSUTOMU
IPC分类号： G05B15/02 , H04B15/00
摘要： PURPOSE:To prevent equipment to be controlled from being miscontrolled even if a noise appears on a transmission line, etc., by adding and sending out selection control master data, deciding whether the selection control master data satisfies control conditions, and regenerating a control request signal only when the control conditions are satisfied. CONSTITUTION:Plural-bit selection control master data which is common to all control request signals and corresponds to the control conditions is added to select bit data corresponding to a control request signal from a central controller 1 and those are supplied to an actual site controller 5 through a center- side scanning transmitter 2, a scanning transmission line 3, and an actual-site side scanning transmitter 4. Further, when the selection control master data satisfies the control conditions, the actual-site controller 5 controls actual-site equipment. Therefore, even when plural dummy data are supplied to the actual- site side scanning transmitter 4, a control signal is not outputted from the actual-site side canning transmitter 4. Consequently, the actual-site equipment is prevented from being miscontrolled.

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