会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 6. 发明专利
    • Semiconductor device and method of manufacturing the same
    • 半导体器件及其制造方法
    • JP2011061071A
    • 2011-03-24
    • JP2009210548
    • 2009-09-11
    • Toshiba Corp株式会社東芝
    • AKIYAMA NAOINUMIYA SEIJI
    • H01L21/8238H01L21/28H01L21/283H01L27/092H01L29/423H01L29/49H01L29/78
    • H01L29/1054H01L21/28088H01L21/823807H01L21/823857H01L29/4966H01L29/513H01L29/517H01L29/518H01L29/78
    • PROBLEM TO BE SOLVED: To provide a semiconductor device which contains CMOSFET having work functions suitable for PMOS and NMOS, using a gate insulating film of high dielectric constant, and to provide a method for manufacturing the device.
      SOLUTION: The manufacturing method of a semiconductor device includes a step for forming P-type and N-type regions, insulated from each other by an element separation region, on a main surface of a semiconductor substrate; a step for forming a first insulating film comprising a silicon oxide film or silicon oxide nitride film on the P-type and N-type regions; a step for forming a lanthanum oxide film on the first insulating film on the P-type region; a step for forming a second insulating film containing hafnium or zirconium on the lanthanum oxide film on the P-type region and the first insulating film on the N-type region; and a step for forming a titanium nitride film, which satisfies x/y x N
      y on the second insulating film.
      COPYRIGHT: (C)2011,JPO&INPIT
    • 要解决的问题:提供一种包含具有适用于PMOS和NMOS的功函数的CMOSFET的半导体器件,使用高介电常数的栅极绝缘膜,并提供一种制造器件的方法。 解决方案:半导体器件的制造方法包括在半导体衬底的主表面上形成由元件分离区彼此绝缘的P型和N型区的步骤; 在P型和N型区域上形成包含氧化硅膜或氧化硅氮化物膜的第一绝缘膜的步骤; 在P型区域上的第一绝缘膜上形成氧化镧膜的工序; 在P型区域上的氧化镧膜上形成含有铪或锆的第二绝缘膜和N型区域上的第一绝缘膜的工序; 以及在第二绝缘膜上与Ti x N y 形成满足x / y <1的氮化钛膜的工序。 版权所有(C)2011,JPO&INPIT
    • 7. 发明专利
    • Semiconductor device, and method for manufacturing the same
    • 半导体器件及其制造方法
    • JP2010073865A
    • 2010-04-02
    • JP2008239200
    • 2008-09-18
    • Toshiba Corp株式会社東芝
    • IKENO DAISUKEAOYAMA TOMONORINAKAJIMA KAZUAKIINUMIYA SEIJISHIMIZU TAKASHIKOBAYASHI TAKUYA
    • H01L21/8238H01L21/28H01L27/092H01L29/423H01L29/49H01L29/78
    • H01L21/823807H01L21/823828
    • PROBLEM TO BE SOLVED: To provide a semiconductor device and a method for manufacturing the same wherein an effective work function of a gate electrode can be stably set at a value near mid-gap of an Si band gap, in the semiconductor device having an NMOS and a PMOS such as an NMOSFET and a PMOSFET.
      SOLUTION: The semiconductor device is configured by including: a semiconductor substrate which has a p-type diffusion layer and an n-type diffusion layer separated by an element isolating means; a gate insulating film formed on each of the p-type diffusion layer and the n-type diffusion layer of the semiconductor substrate; the gate electrode containing a metal film formed on the gate insulating film; a Ge inclusion formed at an interface between the gate insulating film and the metal film; and a silicon-contained layer formed on the metal film.
      COPYRIGHT: (C)2010,JPO&INPIT
    • 要解决的问题:为了提供半导体器件及其制造方法,其中在半导体器件中可以将栅电极的有效功函数稳定地设定在接近中间间隙的值 具有NMOS和诸如NMOSFET和PMOSFET的PMOS。 解决方案:半导体器件通过包括:半导体衬底,其具有由元件隔离装置隔开的p型扩散层和n型扩散层; 形成在半导体衬底的p型扩散层和n型扩散层中的每一个上的栅极绝缘膜; 所述栅极电极含有形成在所述栅极绝缘膜上的金属膜; 形成在栅极绝缘膜和金属膜之间的界面处的Ge夹杂物; 以及形成在金属膜上的含硅层。 版权所有(C)2010,JPO&INPIT
    • 9. 发明专利
    • Method and apparatus for manufacturing semiconductor device
    • 制造半导体器件的方法和装置
    • JP2006128380A
    • 2006-05-18
    • JP2004314154
    • 2004-10-28
    • Toshiba Corp株式会社東芝
    • SEKINE KATSUYUKIINUMIYA SEIJISATO MOTOYUKIKANEKO AKIOEGUCHI KAZUHIRO
    • H01L21/31H01L21/265H01L21/316H01L21/318H05H1/00
    • H01L21/67253H01J37/32935H01L21/67069H01L22/14
    • PROBLEM TO BE SOLVED: To provide a manufacturing method and a manufacturing apparatus of a semiconductor device capable of suppressing variations in film thickness and the amount of impurities between semiconductor wafers and between lots for obtaining stable element characteristics in plasma surface reforming and an impurity introduction process. SOLUTION: There are provided: a process for measuring the light intensity of at least one kind of wavelength in light emitted from plasma, or incidence power and reflection power in addition to the light intensity when one of nitriding treatment, oxidation treatment, and impurity introduction is performed onto the surfaces of a plurality of semiconductor substrates; a process for calculating exposure time for performing exposure to plasma for each semiconductor substrate, based on the light intensity, or the light intensity, the incident power, and the reflection power obtained by the measurement; and a process for exposing each semiconductor substrate to plasma based on the calculated exposure time to perform one of the nitriding treatment, oxidation treatment, and impurity introduction. COPYRIGHT: (C)2006,JPO&NCIPI
    • 解决的问题:提供能够抑制等离子体表面改性中的稳定元素特性的膜厚变化和半导体晶片间杂质量之间的杂质的制造方法和制造装置,以及 杂质引入过程。 解决方案:提供了一种用于测量从等离子体发射的光中的至少一种波长的光强度或除了光强度之外的入射功率和反射功率的过程,当氮化处理,氧化处理, 并且在多个半导体基板的表面上进行杂质引入; 基于通过测量获得的光强度或光强度,入射功率和反射功率,计算用于对每个半导体衬底进行等离子体曝光的曝光时间的处理; 以及基于所计算的曝光时间将每个半导体衬底暴露于等离子体以进行氮化处理,氧化处理和杂质引入之一的工艺。 版权所有(C)2006,JPO&NCIPI