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1. 发明专利

JPH0799221A BURN-IN TEST CIRCUIT FOR SEMICONDUCTOR DEVICE AND METHOD THEREFOR 失效
公开(公告)号：JPH0799221A
公开(公告)日：1995-04-11
申请号：JP9357593
申请日：1993-03-29
申请人： TEXAS INSTRUMENTS JAPAN , HITACHI LTD
发明人： NASU TAKUMI , YAMAGUCHI YASUNORI , MATSUURA NOBUMI , IWAI HIDETOSHI , SAKUTA TOSHIYUKI
IPC分类号： G01R31/26 , G01R31/28 , H01L21/66
摘要： PURPOSE:To apply to an insulation film field stress equivalent to or more than that by the conventional method through burn-in for a short period by accelerating the field stress between multiple-level conductive layers mutually, between a conductive layer and an accumulation electrode and between the level conductive layers for the conductive layer mutually. CONSTITUTION:The potential is fixed at 0V in the parts between a bit line 23 of a first metallic layer level and a Y line 24 of a second metallic layer level, between an accumulation electrode 22 and the line 23 of the first metallic layer level, and between an accumulation node 21 and the electrode 22. Therefore, since the stress status does not change at all, any one is selected and kinds of stress cycles are combined for a short burn-in period, so that effective field stress can be made to work to the insulation films 15, 16, 17 and 18 of respective layers.

2. 发明专利

JPH06151435A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH06151435A
公开(公告)日：1994-05-31
申请号：JP32726492
申请日：1992-11-12
申请人： TEXAS INSTRUMENTS JAPAN , HITACHI LTD
发明人： NASU TAKUMI , SUZUKI TOMOHIRO , ITO YUTAKA , IWAI HIDETOSHI , SAKUTA TOSHIYUKI
IPC分类号： H01L23/52 , H01L21/3205 , H01L23/522 , H01L23/552
摘要： PURPOSE:To provide a semiconductor device of a structure, wherein a potential fluctuation in a semiconductor substrate is prevented from being superposed on a power wiring as noise, by a method wherein a shielding wiring is provided between the semiconductor substrate and the power wiring for feeding a power potential or a ground potential. CONSTITUTION:A shielding wiring 1 is provided between a Vss wiring 2 for feeding a ground potential to each circuit on a semiconductor chip and a substrate 7. This shielding wiring 1 is connected to a lead frame 18 for ground via a wiring 4 in an M1 chip, a wiring 5 in an M2 chip, connection members 40, a bonding pad 3 and a bonding wire 8. As a coupling impedance (Most of the impedance is an electrostatic capacity Css.) between the wiring 1 and the substrate 7 is large and a coupling impedance (Most of the impedance is a junction capacitance D.) between the wiring 2 and the substrate 7 is small, noise due to a potential fluctuation in the substrate 7 propagates to the wiring 1 and does hardly propagate to the wiring 2.

3. 发明专利

JPH0620471A DYNAMIC RAM 失效
公开(公告)号：JPH0620471A
公开(公告)日：1994-01-28
申请号：JP19660592
申请日：1992-06-30
申请人： HITACHI LTD , TEXAS INSTRUMENTS JAPAN
发明人： SAKUTA TOSHIYUKI , SUZUKI TOMOHIRO , IIZUKA YURIKO
IPC分类号： G11C11/407 , G11C5/14 , G11C11/401
摘要： PURPOSE:To reduce the pulse signal frequency in the operation mode compensating the leak current to reduce the power consumption by switching the pulse signal frequency inputted to a pumping circuit by the operation mode to adjust the current supply capability. CONSTITUTION:Except at the time of power-on or burn-in test, a selector SEL is switched to give a low current supply capability compensating the substrate leak current to a pumping circuit PUMP 2. An oscillating circuit OSC 3 steadily generates about 50kHz low pulse signal frequency. Since the PUMP 2 having a large capacitor constituting a main circuit is used to compensate the leak current, the frequency is reduced to such a low frequency by the large capacitor capacity when the same current supply capacity is set. The OSC 3 is steadily operated, and consequently, the current consumption is reduced because the oscillation frequency is low. Since the current consumption of the a CMOS circuit is proportional to the operation frequency, the current consumption of the oscillating circuit is reduced.

4. 发明专利

JPH0621320A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0621320A
公开(公告)日：1994-01-28
申请号：JP19660492
申请日：1992-06-30
申请人： HITACHI LTD , TEXAS INSTRUMENTS JAPAN
发明人： ITO YUTAKA , SAKUTA TOSHIYUKI , NASU TAKUMI
IPC分类号： H01L23/12 , H01L23/495 , H01L23/50 , H01L23/64
摘要： PURPOSE:To make it possible to reduce propagation to the input side of noises generated at the operation of an output circuit by supplying power source voltage and the earth electric potential of a circuit through outer terminals consisting of LOC lead frames which are separated individually. CONSTITUTION:Power source supply wires 2, 3 for an input circuit are connected to power source supply wires 12, 13 of an inside circuit, and to bus bar lead wires 18, 19, which are connected to power source wires 14, 15, through resistor 1 and bonding wire 11 respectively. Owing to the insertion of such a resistance element, noises generated in the output circuit can be suppressed to invade on the side of the input circuit, while restraining, in direct current, ununiformity of the electric potential at power source pins. As a result, operation margin in the input circuit can be obtained, while performing simultaneous output of multiple pits to meet the demand for a larger scale circuit.

5. 发明专利

JPH0757463A VOLTAGE GENERATION CIRCUIT AND 1/2 VDD GENERATION CIRCUIT 失效
公开(公告)号：JPH0757463A
公开(公告)日：1995-03-03
申请号：JP22509493
申请日：1993-08-18
申请人： TEXAS INSTRUMENTS JAPAN , HITACHI LTD
发明人： SUZUKI TOMOHIRO , SAKUTA TOSHIYUKI
IPC分类号： G01R19/00 , G05F3/24 , G05F3/26 , G11C11/407 , H03G3/02 , H03K19/00
摘要： PURPOSE:To remarkably improve the ability of current supply or current lead in and speed of a voltage generation circuit or a 1/2 VDD generation circuit. CONSTITUTION:When an output voltage VOUT is dropped rapidly from a reference value 1/2 VDD, and becomes lower than limit allowable voltage level VM-, a N type MOS transistor MN5A in an output voltage detection circuit 14 is turned on. The potential of a gate terminal of a P type MOS transistor MP6A in a digital output circuit 16 is pulled up to the level of the output voltage VOUT through the turned on transistor MN5A, and the P type MOS transistor MP6A is turned on in a nearly perfect saturation area. A large amt. of current flows vigorously from a power source terminal 18 to an output terminal 22 side, that is, a load circuit side through the P type MOS transistor MP6A turned on in the saturation area, the drop fluctuation of the output voltage VOUT is stopped rapidly, and the voltage VOUT is restored to a normal level in a short time.

6. 发明专利

JPH06282985A DYNAMIC TYPE RAM 失效
公开(公告)号：JPH06282985A
公开(公告)日：1994-10-07
申请号：JP9526093
申请日：1993-03-30
申请人： HITACHI LTD , TEXAS INSTRUMENTS JAPAN
发明人： SAKUTA TOSHIYUKI , SUZUKI TOMOHIRO
IPC分类号： G11C11/403 , G11C11/406
摘要： PURPOSE:To simplify a circuit by sharing a counter output identifying circuit and controlling an output identification and a counter circuit by means of the identification output and a control signal. CONSTITUTION:For the measuring of the number of refreshing times, the number of refreshing times for carrying out a refreshing operation once for the number of maximum refreshing times, that is, all memory cells is measured. In addition to bit for measuring refreshing times, bit for measuring pausing period of time is provided. The counted output of the counter circuit is inputted to three counter output identification circuits and at each of them, a mode entry time measuring output ME, a refreshing times measuring output RC and a pause limit time measuring output PL are formed. In the respective output identification circuit, initial value setting huses are included. These are corresponded to time differences in the oscillation pulse of a basic oscillator by the specification of the dynamic type RAM having them and a manufacturing process. Thus, the circuit is simplified.

7. 发明专利

JPH04222989A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH04222989A
公开(公告)日：1992-08-12
申请号：JP41442590
申请日：1990-12-26
申请人： HITACHI LTD
发明人： SAKUTA TOSHIYUKI , ITO KAZUYA , ISHIHARA MASAMICHI
IPC分类号： G11C11/401 , G11C11/409 , H01L25/04 , H01L25/18
摘要： PURPOSE:To equalize the generated heat and to prevent the breakage due to the distortion generated from it by operating the incorporated memory in parallel in the semiconductor integrated circuit embedding plural chips in one piece of package. CONSTITUTION:Two pieces of DRAM chips 2, 3 can be selected in parallel. The output buffer 21 to enable to prohibit the data output operation is provided, even when it is in a data reading mode, and a column address decorder 17 to enable to prohibit the column selective signal output operation is provided, even when it is in the data writing mode. The signal phij to control those is subjected to logical inversion to both chips 2, 3 with a bonding option mutually and is supplied to both chips 2, 3. In the access operation, both chips 2, 3 are brought into parallel operation to consume nearly the same electric power and the substantial data read-out with the outside or the write-in is performed only with one side of the chip. Thus the breakage of the passivation film due to the non-equilibrium of the thermal stress is prevented.

8. 发明专利

JPH047867A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH047867A
公开(公告)日：1992-01-13
申请号：JP10862190
申请日：1990-04-26
申请人： HITACHI LTD
发明人： OGUCHI SATOSHI , ISHIHARA MASAMICHI , ITO KAZUYA , MURAKAMI HAJIME , ANJO ICHIRO , SAKUTA TOSHIYUKI
IPC分类号： H01L25/00 , H01L23/50 , H01L25/04 , H01L25/065 , H01L25/07 , H01L25/18 , H01L27/10
摘要： PURPOSE:To improve manufacturing yield and intend cost optimization, by dividing a semiconductor device with a specified function based on the optimum design into a plurality of semiconductor elements, connecting them directly by using bonding pads, wires, leads, etc., and reconstituting a semiconductor device with a specified function. CONSTITUTION:A 64 Mbit DRAM 1 with a specified function based on the optimum design is divided into two 32 Mbit DRAM subchips 1A and 1B, which are electrically connected so as to constitute the 64 Mbit DRAM 1 with a function before division which is based on the optimum design. Thus a laminated layer structure is completed through direct electric connection using bonding pads, wires, leads, etc., without interposing a wiring board and the like. Thereby a semiconductor device based on the optimum design can be easily obtained, and cost optimization can be intended.

9. 发明专利

JPH02246149A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR REMEDYING DEFECT THEREOF 失效
公开(公告)号：JPH02246149A
公开(公告)日：1990-10-01
申请号：JP6583989
申请日：1989-03-20
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI DEVICE ENG
发明人： SAKUTA TOSHIYUKI , ISHIHARA MASAMICHI , MIYAZAWA KAZUYUKI , HIROKI MASANORI , IWAI HIDETOSHI , NAKAMURA TAKASHI , TAKAHASHI YASUSHI , MAEDA TOSHIO , MATSUURA NOBUMI , HORI RYOICHI , SASAKI TOSHIO , SAKAI OSAMU , UCHIYAMA HIROYUKI
IPC分类号： G11C29/00 , G11C11/401 , G11C11/406 , G11C29/04 , H01L21/82 , H01L27/10
摘要： PURPOSE:To simplify and rationalize a layout by a method wherein a circuit having a RAM function is formed as a macrocell and a plurality of macrocells constitute a semiconductor storage circuit of a large storage capacity. CONSTITUTION:In this RAM, a plurality of memory blocks which has been formed as macrocells are arranged in a matrix manner. Sixteen memory blocks of about 4 Mbits each are arranged in four rows and four columns and have a large storage capacity of about 64 Mbits as a whole. One memory block constituted as the macrocell is provided with the following: a row-based address decoder which receives an address signal supplied through a timing/address generation circuit which have been made common; an address selection circuit composed of a word-line drive circuit, a column-based address decoder, a column selection-line drive circuit or the like; a timing generation circuit which generates a time-series timing pulse when an internal operation is required according to a memory array and an operating mode; a timing generation circuit for a selected memory cell; an input/output circuit which executes a write/readout operation of a data for the selected memory cell.

10. 发明专利

JPS6453399A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS6453399A
公开(公告)日：1989-03-01
申请号：JP21118587
申请日：1987-08-25
申请人： HITACHI LTD
发明人： SAKUTA TOSHIYUKI , TAKAHASHI YASUSHI , ISHIHARA MASAMICHI
IPC分类号： G11C11/413 , G11C11/34 , G11C11/401 , G11C11/409 , G11C29/00 , G11C29/34
摘要： PURPOSE:To improve testing efficiency, by deciding the normal/defective condition of plural memory cells comprehensively by plural memory cell data initialized at prescribed levels based on the coincidence/non-coincidence between an obtained pair of common data lines. CONSTITUTION:Data with the same level are written on all memory cells MC in advance in testing, and after that, when second switching devices Q6 and Q7 are selected comprehensively at every selection of word lines W1, W2..., the levels of a pair of common data lines RCD and the inverse of RCD are set as complementary levels corresponding to a write level in case of including no defective memory cell, however, in case of including a defective memory cell, they are set as in-phase levels. It is possible to decide the normal/defective condition of all of the memory cells MC in a direction of word line by one time of selection operation of the word lines W1, W2... by deciding a difference in the above case. In such a way, it is possible to improve the testing efficiency.

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