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1. 发明专利

JP2012015229A Method of producing silicon carbide semiconductor device 审中-公开
标题翻译：生产碳化硅半导体器件的方法
公开(公告)号：JP2012015229A
公开(公告)日：2012-01-19
申请号：JP2010148530
申请日：2010-06-30
申请人： Sumitomo Electric Ind Ltd , 住友電気工業株式会社
发明人： CHIKUNO TAKASHI , TAMASO HIDETO , SHIOMI HIROSHI
IPC分类号： H01L21/265 , C23C16/511 , C23C16/56
摘要： PROBLEM TO BE SOLVED: To provide a method of producing a silicon carbide semiconductor device in which there is no occurence of roughness over the entire surface of a silicon carbide wafer.SOLUTION: A method of producing a silicon carbide semiconductor device comprises a step of performing ion injection of an impurity 30i into a silicon carbide wafer 10, a step of forming a diamond layer 40 on the silicon carbide wafer 10 into which ion injection of the impurity 30i is performed and a step of performing a heat treatment to the silicon carbide wafer 10 on which the diamond layer 40 is formed so as to form an impurity region 30 in which the impurity 30i is activated in the silicon carbide wafer 10.
摘要翻译：要解决的问题：提供一种在碳化硅晶片的整个表面上不发生粗糙度的碳化硅半导体器件的制造方法。解决方案：制造碳化硅半导体器件的方法包括：将杂质30i离子注入到碳化硅晶片10中的步骤，在碳化硅晶片10上形成金刚石层40的步骤，其中离子注入执行杂质30i的步骤和对其上形成有金刚石层40的碳化硅晶片10进行热处理以形成其中在碳化硅晶片10中激活杂质30i的杂质区30的步骤。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2011071195A Method of manufacturing semiconductor substrate 审中-公开
标题翻译：制造半导体基板的方法
公开(公告)号：JP2011071195A
公开(公告)日：2011-04-07
申请号：JP2009219068
申请日：2009-09-24
申请人： Sumitomo Electric Ind Ltd , 住友電気工業株式会社
发明人： SASAKI MAKOTO , HARADA MAKOTO , WADA KEIJI , TAMASO HIDETO , NAMIKAWA YASUO
IPC分类号： H01L21/02 , H01L21/336 , H01L29/12 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor substrate for efficiently manufacturing a semiconductor device using SiC.
SOLUTION: The method includes preparing a first silicon carbide substrate 11 having a first surface F1 and a first backside B1 opposing to each other and having a single crystal structure, and a second silicon carbide substrate 12 having a second surface F2 and a second backside B2 opposing to each other and having a single crystal structure. The first and second silicon carbide substrates 11, 12 are disposed so that the first and second backsides B1, B2 can be directed in the same direction. After a step of disposition, a connection layer 30 containing carbon, which is bonded to the first and second backsides B1, B2 so as to connect the first and second backsides B1, B2, is formed.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造半导体衬底的方法，用于使用SiC有效地制造半导体器件。解决方案：该方法包括制备具有彼此相对并具有单晶结构的第一表面F1和第一背面B1的第一碳化硅衬底11和具有第二表面F2和第二表面F2的第二碳化硅衬底12 第二背面B2彼此相对并具有单晶结构。第一和第二碳化硅衬底11,12被布置成使得第一和第二背面B1，B2可以朝向相同的方向。在配置步骤之后，形成包含碳的连接层30，其连接到第一和第二背面B1，B2以连接第一和第二背面B1，B2。版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2009200326A Manufacturing method of silicon carbide semiconductor device, and silicon carbide semiconductor device 有权
标题翻译：硅碳化硅半导体器件的制造方法和碳化硅半导体器件
公开(公告)号：JP2009200326A
公开(公告)日：2009-09-03
申请号：JP2008041658
申请日：2008-02-22
申请人： Sumitomo Electric Ind Ltd , 住友電気工業株式会社
发明人： TAMASO HIDETO , MASUDA KENRYO
IPC分类号： H01L21/28 , H01L21/336 , H01L21/337 , H01L21/338 , H01L29/78 , H01L29/808 , H01L29/812
CPC分类号： H01L21/0485
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a silicon carbide semiconductor device which can improve reliability; and a silicon carbide semiconductor device.
SOLUTION: This manufacturing method of a silicon carbide semiconductor device includes the following processes of: first preparing a silicon carbide semiconductor layer 110 including a principal surface 110a; doping silicon in the principal surface 110a of the silicon carbide semiconductor layer 110 to form a high-concentration region 115 high in silicon concentration relative to a region without doping silicon in the silicon carbide semiconductor layer 110; forming metal layers 143 and 144 containing a material producing a compound with silicon at positions in contact with the high-concentration region 115; and heat-treating the metal layers 143 and 144 to form electrodes containing the compound.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供可提高可靠性的碳化硅半导体器件的制造方法; 和碳化硅半导体器件。解决方案：该碳化硅半导体器件的制造方法包括以下处理：首先制备包括主面110a的碳化硅半导体层110; 在碳化硅半导体层110的主表面110a中掺杂硅，以形成相对于在碳化硅半导体层110中不掺杂硅的区域，硅浓度高的高浓度区域115; 在与高浓度区域115接触的位置处形成含有与硅化合物的材料的金属层143和144; 并且对金属层143和144进行热处理以形成含有该化合物的电极。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2009188100A Method for manufacturing silicon carbide semiconductor device 审中-公开
标题翻译：制造碳化硅半导体器件的方法
公开(公告)号：JP2009188100A
公开(公告)日：2009-08-20
申请号：JP2008025175
申请日：2008-02-05
申请人： Sumitomo Electric Ind Ltd , 住友電気工業株式会社
发明人： TAMASO HIDETO
IPC分类号： H01L21/28 , H01L21/329 , H01L21/337 , H01L21/768 , H01L29/417 , H01L29/78 , H01L29/808 , H01L29/861
CPC分类号： H01L21/0485
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a silicon carbide semiconductor device, capable of raising adhesiveness between an electrode and wiring when forming the wiring.
SOLUTION: The method for manufacturing silicon carbide semiconductor device 100a includes: a process for preparing a silicon carbide semiconductor layer 110; a process for forming a metallic layer on the surface of the silicon carbide semiconductor layer 110; a process for forming the electrode 150 by thermally processing the metallic layer; and a process for performing etching to remove carbon on the surface of the electrode 150. In the process for forming the metallic layer, the metallic layer is formed, which is more reactive with silicon than carbon at temperature to thermally process the metallic layer.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造碳化硅半导体器件的方法，其能够在形成布线时提高电极和布线之间的粘附性。解决方案：制造碳化硅半导体器件100a的方法包括：制备碳化硅半导体层110的工艺; 在碳化硅半导体层110的表面上形成金属层的工艺; 通过热处理金属层形成电极150的工艺; 以及用于进行蚀刻以除去电极150的表面上的碳的方法。在形成金属层的工艺中，形成金属层，该金属层在对金属层进行热处理的温度下比碳更具反应性。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2009117527A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2009117527A
公开(公告)日：2009-05-28
申请号：JP2007287445
申请日：2007-11-05
申请人： Sumitomo Electric Ind Ltd , 住友電気工業株式会社
发明人： TAMASO HIDETO , HARADA MAKOTO
IPC分类号： H01L21/3065 , H01L21/337 , H01L29/78 , H01L29/808
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, in which manufacturing process can be simplified by employing TaC as a material for a mask used to etch SiC.
SOLUTION: A method of manufacturing an MOSFET as a semiconductor device includes: a substrate preparing step and an n-type SiC layer forming step of preparing an n-type SiC layer as an SiC member; a TaC film forming step of forming a TaC film on the n-type SiC layer; a TaC mask forming step of shaping the TaC film in a mask shape; and an n-type SiC layer etching step of using the TaC film shaped in the mask shape as a mask to etch the n-type SiC layer. In an n-type SiCz layer etching step, the n-type SiC layer is etched through dry etching using a mixed gas comprising a gas containing F and a gas containing O.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供一种制造半导体器件的方法，其中可以通过使用TaC作为用于蚀刻SiC的掩模的材料来简化制造工艺。解决方案：制造作为半导体器件的MOSFET的方法包括：制备n型SiC层作为SiC构件的衬底制备步骤和n型SiC层形成步骤; 在n型SiC层上形成TaC膜的TaC膜形成工序; 形成掩模形状的TaC膜的TaC掩模形成步骤; 以及使用掩模形状的TaC膜作为掩模的n型SiC层蚀刻步骤来蚀刻n型SiC层。在n型SiCz层蚀刻步骤中，使用包含含有F的气体和含有O的气体的混合气体通过干蚀刻蚀刻n型SiC层。（C）2009，JPO＆INPIT

6. 发明专利

JP2012114210A Method of manufacturing silicon carbide semiconductor device and manufacturing apparatus for silicon carbide semiconductor device 审中-公开
标题翻译：硅碳化硅半导体器件的制造方法和硅碳化硅半导体器件的制造装置
公开(公告)号：JP2012114210A
公开(公告)日：2012-06-14
申请号：JP2010261323
申请日：2010-11-24
申请人： Sumitomo Electric Ind Ltd , 住友電気工業株式会社
发明人： MIYAZAKI TOMIHITO , SHIOMI HIROSHI , TAMASO HIDETO , MASUDA TAKEYOSHI
IPC分类号： H01L21/304 , H01L21/28 , H01L21/306 , H01L21/3065 , H01L21/31 , H01L21/336 , H01L29/12 , H01L29/78
CPC分类号： H01L29/66068 , H01L21/02046 , H01L21/02052 , H01L21/02057 , H01L21/0209 , H01L21/02236 , H01L21/049 , H01L21/28238 , H01L29/1608 , H01L29/7802
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a SiC semiconductor device capable of minimizing problems associated with chemical liquid and capable of improving cleaning effect, and to provide a manufacturing apparatus for the SiC semiconductor device.SOLUTION: A method of manufacturing a SiC semiconductor device comprises the steps of: forming an oxide film on a surface of SiC (a step S3); and removing the oxide film (a step S5). The formation step of the oxide film (the step S3) uses an ozone gas. The removal step of the oxide film (the step S5) preferably uses halogen plasma or hydrogen plasma.
摘要翻译：解决的问题：提供一种能够使与化学液体相关的问题最小化并能够提高清洗效果的SiC半导体器件的制造方法，提供一种SiC半导体器件的制造装置。解决方案：制造SiC半导体器件的方法包括以下步骤：在SiC的表面上形成氧化膜（步骤S3）; 并除去氧化膜（步骤S5）。氧化膜的形成步骤（步骤S3）使用臭氧气体。氧化膜的除去步骤（步骤S5）优选使用卤素等离子体或氢等离子体。版权所有（C）2012，JPO＆INPIT

7. 发明专利

JP2011258768A Silicon carbide substrate, substrate with epitaxial layer, semiconductor device and method of manufacturing silicon carbide substrate 审中-公开
标题翻译：硅碳化物衬底，具有外延层的衬底，半导体器件和制造碳化硅衬底的方法
公开(公告)号：JP2011258768A
公开(公告)日：2011-12-22
申请号：JP2010132253
申请日：2010-06-09
申请人： Sumitomo Electric Ind Ltd , 住友電気工業株式会社
发明人： SHIOMI HIROSHI , TAMASO HIDETO , HARADA MAKOTO , TSUNO TAKASHI , NAMIKAWA YASUO
IPC分类号： H01L21/20 , C30B29/36 , H01L21/02 , H01L21/205 , H01L29/12 , H01L29/47 , H01L29/78 , H01L29/872
CPC分类号： H01L21/02631 , H01L21/02378 , H01L21/02447 , H01L21/02529 , H01L21/02658 , H01L21/02664 , H01L21/046 , H01L21/0495 , H01L29/04 , H01L29/1608 , H01L29/6606 , H01L29/66068 , H01L29/7802
摘要： PROBLEM TO BE SOLVED: To provide a silicon carbide substrate which can reduce on-resistance, and to provide a substrate with an epitaxial layer, a semiconductor device and a method of manufacturing a silicon carbide substrate.SOLUTION: The silicon carbide substrate 10 having a principal face comprises an SiC single crystal substrate 1 formed at least partially on the principal face, and a base member 20 arranged to surround the periphery of the SiC single crystal substrate 1. The base member 20 includes a boundary region 11 and an underlying region 12. The boundary region 11 is contiguous to the SiC single crystal substrate 1 in the direction along the principal face, and has a grain boundary internally. The underlying region 12 is contiguous to the SiC single crystal substrate 1 in the direction perpendicular to the principal face, and has an impurity concentration higher than that in the SiC single crystal substrate 1.
摘要翻译：要解决的问题：提供一种可以降低导通电阻的碳化硅衬底，以及提供具有外延层的衬底，半导体器件和制造碳化硅衬底的方法。解决方案：具有主面的碳化硅衬底10包括至少部分地形成在主面上的SiC单晶衬底1和布置成围绕SiC单晶衬底1的周围的基底构件20.基底构件20包括边界区域11和下面的区域12.边界区域11沿着主面的方向与SiC单晶衬底1邻接，并且在内部具有晶界。底层区域12在与主面垂直的方向上与SiC单晶衬底1邻接，杂质浓度高于SiC单晶衬底1中的杂质浓度。（C）2012，JPO＆INPIT

8. 发明专利

JP2010166024A Semiconductor device, and method for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010166024A
公开(公告)日：2010-07-29
申请号：JP2009244596
申请日：2009-10-23
申请人： Sumitomo Electric Ind Ltd , 住友電気工業株式会社
发明人： FUJIKAWA KAZUHIRO , TAMASO HIDETO , HARADA MAKOTO , NAMIKAWA YASUO
IPC分类号： H01L21/337 , H01L21/265 , H01L21/338 , H01L29/47 , H01L29/808 , H01L29/812 , H01L29/872
CPC分类号： H01L29/66068 , H01L21/0465 , H01L29/1066 , H01L29/1608 , H01L29/8083
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of obtaining surely a characteristic to be inherently obtained by adopting SiC as a raw material, and to provide a manufacturing method thereof.
SOLUTION: An JFET 1 has a wafer 10 with at least an upper face 14A formed with silicon carbide, and a gate contact electrode 21 formed on the upper face 14A. The wafer 10 includes the first p-type region 16 that is an ion implantation region formed to include the upper face 14A. The first p-type region 16 includes a base region 16A arranged to include the upper face 14A, and a projected region 16B. The width w
1 in a direction along the upper face 14A is wider than the width w
2 of the projected region 16B, in the base region 16A. The gate contact electrode 21 is arranged in contact with the first p-type region 16, to overlap the whole thereof with the first p-type region 16 in top view.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以获得通过以SiC为原料固有地获得的特性的半导体器件，并提供其制造方法。解决方案：JFET 1具有至少形成有碳化硅的上表面14A和形成在上表面14A上的栅极接触电极21的晶片10。晶片10包括形成为包括上表面14A的离子注入区域的第一p型区域16。第一p型区域16包括布置成包括上表面14A的基部区域16A和突出区域16B。沿着上表面14A的方向上的宽度w 1 比基准区域16A中的投影区域16B的宽度w SB <2>更宽。栅极接触电极21被布置成与第一p型区域16接触，从而与顶部视图中的第一p型区域16重叠。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP2009177006A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2009177006A
公开(公告)日：2009-08-06
申请号：JP2008014964
申请日：2008-01-25
申请人： Sumitomo Electric Ind Ltd , 住友電気工業株式会社
发明人： ITO SATOMI , TAMASO HIDETO , MASUDA KENRYO
IPC分类号： H01L21/266 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device capable of improving a manufacturing yield of the semiconductor device, and reducing variations in characteristics of the semiconductor devices.
SOLUTION: This manufacturing method of a semiconductor device includes processes of: forming a first ion implantation mask on the surface of a semiconductor having irregularity; forming a second ion implantation mask on a surface of the first ion implantation mask; forming photoresist on a surface of the second ion implantation mask; removing a part of the photoresist to expose the surface of the second ion implantation mask; exposing the surface of the first ion implantation mask by removing the exposed part of the second ion implantation mask by etching; and removing an etching residual part remaining on the exposed part of the first ion implantation mask by etching after a first etching process.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够提高半导体器件的制造成品率并减少半导体器件的特性变化的半导体器件的制造方法。解决方案：这种半导体器件的制造方法包括以下处理：在具有不规则性的半导体的表面上形成第一离子注入掩模; 在所述第一离子注入掩模的表面上形成第二离子注入掩模; 在所述第二离子注入掩模的表面上形成光致抗蚀剂; 去除所述光致抗蚀剂的一部分以暴露所述第二离子注入掩模的表面; 通过蚀刻去除第二离子注入掩模的暴露部分来暴露第一离子注入掩模的表面; 以及在第一蚀刻工艺之后通过蚀刻去除残留在第一离子注入掩模的暴露部分上的蚀刻残留部分。版权所有（C）2009，JPO＆INPIT

10. 发明专利

JP2009059803A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2009059803A
公开(公告)日：2009-03-19
申请号：JP2007224421
申请日：2007-08-30
申请人： Sumitomo Electric Ind Ltd , 住友電気工業株式会社
发明人： TAMASO HIDETO , HOSHINO TAKASHI
IPC分类号： H01L21/337 , H01L21/28 , H01L29/417 , H01L29/423 , H01L29/808
摘要： PROBLEM TO BE SOLVED: To make small the temperature dependency of the resistance value of a semiconductor device controlling a flow of a current using a depletion layer.
SOLUTION: A JFET 10 satisfies T
ref ch-min ≤t
ch ≤t
ch-max , where t
ch is a channel thickness which is the thickness of a channel region where the flow of the current is controlled using the depletion layer, ε
s the dielectric constant of SiC being a material constituting the channel region, (q) elementary electric charge, N
ch the impurity density of an n-type SiC layer 17 being the impurity density of the channel region, N
g the impurity density of a p
+ ion injected region 21b, T the temperature of the channel region when the JFET 10 is in operation, ϕ
bi (T) the built-in potential of a pn junction, T
ref a reference temperature, α
ch a temperature coefficient associated with mobility of carriers in the channel region, α a temperature coefficient associated with the resistance of the channel region, V
d a voltage applied to a drain electrode 31, and (k) an arbitrary numeral of less than 0.8.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：使得使用耗尽层来控制电流流动的半导体器件的电阻值的温度依赖性变小。解决方案：JFET 10满足T ref ch-min ≤t ch ≤t ch-max ，其中t 是通道厚度，其是使用耗尽层控制电流的通道区域的厚度，ε s 作为构成沟道区域的材料的SiC的介电常数，（q）元素电荷，N沟道区域的杂质浓度的n型SiC层17的杂质浓度N < SB> g 离子注入区域21b的杂质浓度，T是JFET 10工作时的沟道区域的温度，＆lt; SB＆gt; bi＆lt; / SB＆ T）pn结的内置电位，T ref 参考温度，α ch 与通道区域中载流子迁移率相关的温度系数，αa温度与沟道区域的电阻相关联的系数V s施加到漏电极31的电压，以及（k）任意numera l小于0.8。版权所有（C）2009，JPO＆INPIT

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