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1. 发明专利

JP2007311924A Bandwidth analyzing device and method, bandwidth composing device and method, image encoding device and method, image decoding device and method, and program and recording medium 有权
标题翻译：带宽分析装置和方法，带宽组合装置和方法，图像编码装置和方法，图像解码装置和方法以及程序和记录介质
公开(公告)号：JP2007311924A
公开(公告)日：2007-11-29
申请号：JP2006136876
申请日：2006-05-16
申请人： Sony Corp , ソニー株式会社
发明人： FUKUHARA TAKAHIRO , ANDO KATSUTOSHI , NISHIMURA NAOTO , TANAKA YUKI , SHIMURA KATSUJI , TAKAHASHI HIROO
IPC分类号： H03M7/30 , H04N1/41 , H04N19/115 , H04N19/126 , H04N19/60 , H04N19/635
CPC分类号： H04N19/647 , H04N19/80
摘要： PROBLEM TO BE SOLVED: To perform wavelet transformation and wavelet inverse transformation to a moving picture signal in real time. SOLUTION: A band analyzing device 10 performs vertical low-pass analysis filtering and high-pass analysis filtering to line data D12 of N lines at a vertical analysis filter 13, and performs horizontal low-pass analysis filtering and high-pass analysis filtering to low-pass and high-pass components D13 at a horizontal analysis filter 14, thus performing the wavelet transformation to each picture for composing a video signal D10. In this case, the band analyzing device 10 quickens the timing of a current picture and symmetric extension processing in the lower end line of each subband of the current picture, thus completing the wavelet transformation of the current picture before the next picture is inputted. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：实时地对运动图像信号执行小波变换和小波逆变换。解决方案：频带分析装置10对垂直分析滤波器13的N线的线数据D12进行垂直低通分析滤波和高通分析滤波，并执行水平低通分析滤波和高通分析在水平分析滤波器14处对低通和高通分量D13进行滤波，从而对每个图像执行小波变换以构成视频信号D10。在这种情况下，频带分析装置10加速当前图像的每个子带的下限行中的当前图像的定时和对称扩展处理，从而在输入下一图像之前完成当前图像的小波变换。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2005107393A Image processing apparatus and method, and program 审中-公开
标题翻译：图像处理设备和方法，程序
公开(公告)号：JP2005107393A
公开(公告)日：2005-04-21
申请号：JP2003343397
申请日：2003-10-01
申请人： Sony Corp , ソニー株式会社
发明人： SHIMURA KATSUJI
IPC分类号： G06T3/00 , G06T5/50 , G09G5/00 , G09G5/377 , H04N5/278 , H04N7/24 , H04N19/00 , H04N19/625 , H04N19/70
摘要： PROBLEM TO BE SOLVED: To easily and appropriately discriminate a display portion and non-display portion of an OSD image in the case the compressed OSD image is decoded and is synthesized to a main image. SOLUTION: The compressed OSD image obtained by compressing the OSD image of, for example, a Y/C4:2:2 structure by a JPEG system is stored into a compressed OSD image data memory 2. The compressed OSD image stored in the compressed OSD image data memory 2 is compressed by the JPEG system with the OSD image formed by setting a decision flag at an MSB of either of a Y component or C component, adding an offset value to the display portion, forming the non-display portion to a prescribed size and incorporating a control parameter therein. The apparatus and method are applicable to, for example, a Camcorder, digital still camera, video recorder or television receiver. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：在压缩的OSD图像被解码并被合成为主图像的情况下，容易且适当地区分OSD图像的显示部分和非显示部分。解决方案：将通过JPEG系统压缩例如Y / C4：2：2结构的OSD图像而获得的压缩OSD图像存储到压缩OSD图像数据存储器2中。压缩的OSD图像存储在压缩OSD图像数据存储器2被JPEG系统压缩，其中OSD图像通过将判定标志设置在Y分量或C分量中的任一个的MSB而形成，将偏移值与显示部分相加，形成非显示部分到规定的尺寸并且在其中并入控制参数。该装置和方法适用于例如摄像机，数码相机，录像机或电视接收机。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2008288833A Information processing apparatus and method, and information processing system 有权
标题翻译：信息处理装置和方法以及信息处理系统
公开(公告)号：JP2008288833A
公开(公告)日：2008-11-27
申请号：JP2007131284
申请日：2007-05-17
申请人： Sony Corp , ソニー株式会社
发明人： FUKUHARA TAKAHIRO , HOSAKA KAZUHISA , SHIMURA KATSUJI , INAGAKI TSUGUNA , TAKAHASHI HIROO
IPC分类号： H04N5/225 , G06F5/14 , G06F13/38 , G06F13/42 , G11B20/10 , H04L12/70 , H04L12/823 , H04L12/835 , H04L12/875 , H04L13/08 , H04N19/00 , H04N19/102 , H04N19/134 , H04N19/152 , H04N19/196 , H04N19/59 , H04N19/63 , H04N19/89 , H04N19/895 , H04N19/91
CPC分类号： H04N5/232 , H04N5/23203 , H04N19/115 , H04N19/132 , H04N19/146 , H04N19/63 , H04N19/645 , H04N21/23406 , H04N21/2383 , H04N21/4382 , H04N21/44004 , H04N21/440254 , H04N21/6377 , H04N21/6379 , H04N21/643 , H04N21/64761 , H04N21/658
摘要： PROBLEM TO BE SOLVED: To easily suppress an increase in unnecessary delay time and to suppress unnecessary deterioration of quality as contents, with data transfer of contents. SOLUTION: When the number of precincts accumulated in a buffer exceeds a predetermined threshold, an output forbidding unit 285 performs bank-over control in response to notice from a number-of-precincts confirmation unit 284 to forbid output of encoded data of the precinct right after a precinct being currently output. The present invention is applicable to, for example, a digital triax system. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了容易地抑制不必要的延迟时间的增加并且通过内容的数据传送来抑制不必要的内容劣化。解决方案：当缓冲器中累积的区数超过预定阈值时，输出禁止单元285响应于来自区号确认单元284的通知而执行重写控制，以禁止编码数据的编码数据的输出目前正在输出区域之后的区域。本发明可应用于例如数字三角系统。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2006072658A Image processing device 有权
标题翻译：图像处理装置
公开(公告)号：JP2006072658A
公开(公告)日：2006-03-16
申请号：JP2004254781
申请日：2004-09-01
申请人： Sony Corp , ソニー株式会社
发明人： SHIMURA KATSUJI , YAMANAKA KATSUHIKO , SUZUKI YOSHIHIRO
IPC分类号： G06T1/60
摘要： PROBLEM TO BE SOLVED: To issue access requests at a frequency depending on a throughput requested by a client without complicating hardware (client) that issues access requests.
SOLUTION: An image processing device has a clock thinning control block 10 for optimizing a bandwidth request for access requests to a memory by distributing the frequency of access requests within a specified period according to the size of image data to be processed by the access requests and processing time allowable to complete the processing.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：根据客户端请求的吞吐量发送访问请求，而不会使发生访问请求的硬件（客户端）复杂化。解决方案：图像处理装置具有时钟稀疏控制块10，用于通过在指定的时间段内分配访问请求的频率来根据要处理的图像数据的大小来分配对存储器的访问请求的带宽请求，访问请求和处理时间可以完成处理。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2004157865A Multiprocessor system 审中-公开
标题翻译：多处理器系统
公开(公告)号：JP2004157865A
公开(公告)日：2004-06-03
申请号：JP2002324183
申请日：2002-11-07
申请人： Sony Corp , ソニー株式会社
发明人： SHIMURA KATSUJI
IPC分类号： G06F15/167 , G06F12/00 , G06F12/06 , G06F15/177
摘要： PROBLEM TO BE SOLVED: To provide a multiprocessor system preventing getting wrong data due to simultaneous access when transferring data between processors. SOLUTION: An access bank control register 111 is provided to which control data is written by a first processor 101 determining which of a first bank 103 or a second bank 104 is accessed by own processor 101 or a second processor 102 and the control data can only be read from the second processor 102. Furthermore, a first memory controller 112 is provided making the first or the second processor possible to access only the first bank 103 which is allotted by the control data set to the access bank control register. Moreover, a second memory controller 113 is provided making the first or the second processor possible to access only the second bank 104 which is allotted by the control data set by the access bank control registor. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种在处理器之间传输数据时由于同时访问而导致错误数据的多处理器系统。解决方案：提供存取库控制寄存器111，由第一处理器101向其写入控制数据，第一处理器101确定由自己的处理器101或第二处理器102访问第一存储体103或第二存储体104中的哪一个，数据只能从第二处理器102读取。此外，提供第一存储器控制器112，使得第一或第二处理器可以仅访问由控制数据集分配给访问组控制寄存器的第一存储体103。此外，提供第二存储器控制器113，使得第一或第二处理器可以仅访问由访问组控制转换器设置的控制数据分配的第二存储体104。版权所有（C）2004，JPO

6. 发明专利

JP2000354246A IMAGE COMPRESSION CONTROLLER AND IMAGE PICKUP SYSTEM USING IT 失效
公开(公告)号：JP2000354246A
公开(公告)日：2000-12-19
申请号：JP16340599
申请日：1999-06-10
申请人： SONY CORP
发明人： SHIMURA KATSUJI , INAGAKI TAKUNARI
IPC分类号： H04N5/225 , G06T9/00 , H03M7/30 , H04N1/41 , H04N19/126 , H04N19/136 , H04N19/189 , H04N19/423 , H04N19/50 , H04N19/625 , H04N19/85 , H04N19/91 , H04N7/32
摘要： PROBLEM TO BE SOLVED: To provide an image compression controller where quantization coefficient control is simplified in the process of image compression and high-speed image compression processing is attained thereby. SOLUTION: The image compression controller is provided with quantization circuits 102, 103 that apply first quantization to an output signal of a DCT circuit 101 on the basis of 1st quantization coefficients QKa, QKb and apply 2nd quantization by one of the circuits on the basis of a 2nd quantization coefficient QKre, with counters 104, 105 that count number of '0s' in the 1st quantization data, a quantization coefficient control circuit 110 that generates a plurality of reference control coefficients and generates a control coefficient on the basis of the count of each counter and a 0 reference value, multipliers 107, 108 that generates the 1st quantization coefficients on the basis of the reference quantization coefficient and a reference control coefficient and generate the 2nd quantization coefficient on the basis of the control coefficient and the reference quantization coefficient and an entropy coding circuit 111 that conducts entropy coding with respect to the 2nd quantization data.

7. 发明专利

JP2002112086A CAMERA SYSTEM, IMAGE ENCODING DEVICE AND IMAGE DECODING DEVICE 失效
公开(公告)号：JP2002112086A
公开(公告)日：2002-04-12
申请号：JP2000296467
申请日：2000-09-28
申请人： SONY CORP
发明人： SHIMURA KATSUJI , YAMAMOTO SHINYA
IPC分类号： G06T1/60 , H03M7/30 , H04N5/225 , H04N5/91 , H04N19/124 , H04N19/126 , H04N19/134 , H04N19/136 , H04N19/176 , H04N19/189 , H04N19/196 , H04N19/423 , H04N19/426 , H04N19/60 , H04N19/625 , H04N19/91 , H04N7/30
摘要： PROBLEM TO BE SOLVED: To provide a camera system capable of inputting rapidly suitably compression encoded static image data by reducing a circuit scale. SOLUTION: At monitor photographing time, a photograph 11 generates thinned data. The thinned data is converted to a digital signal by a signal processor 13, converted into a component signal by a signal processor 14, temporarily stored in a buffer RAM 15, and then displayed on a monitor 34 via an image size converter 19, a video encoder 20 and an A-D converter 21. The displayed thinned image data is encoded by a JPEG compression/elongation processor 16, an encoded amount is calculated, encoded data amount of a full image is predicted, and a quantization table is decided. When a shutter is pressed, the photograph 11 generates the image data of the full pixel, and the JPEG compression/elongation processor 16 encodes the data by the already directly decided quantization table.

8. 发明专利

JP2002094934A SIGNAL PROCESSING UNIT AND CAMERA SYSTEM 失效
公开(公告)号：JP2002094934A
公开(公告)日：2002-03-29
申请号：JP2000283571
申请日：2000-09-19
申请人： SONY CORP
发明人： SHIMURA KATSUJI , YAMAMOTO SHINYA
IPC分类号： G03B19/02 , G06F5/00 , G06F13/36 , G06F13/38 , H04N5/232 , H04N5/91 , H04N101/00
摘要： PROBLEM TO BE SOLVED: To provide a signal processing unit provided with signal processing circuits that can efficiently operate desired processing with a simple configuration and control so as to efficiently execute the desired processing. SOLUTION: A bus bridge circuit 22 in the case of photographing or the like separates a control system bus 20 and a JPEG bus 21 so as to make them acting as independent buses. A camera signal processing system circuit 12 converts image data photographed with a photographing section 11 into a component signal, a JPEG commanding processing circuit 18 applies JPEG compression coding to the component signal, and the resulting signal is stored in a data storage memory 17 via a JPEG bus controller 19 and the JPEG bus 21. Since the control system bus 20 receives no influence at this time, an MPU 23 can independently execute data transfer and transmission of a control signal to each configuration section. When the bus bridge circuit 22 couples the control system bus 20 with the JPEG bus 21 as required, the MPU 23 can access the data storage memory 17.

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