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1. 发明专利

JP2006340018A Drive circuit and imaging apparatus 审中-公开
标题翻译：驱动电路和成像装置
公开(公告)号：JP2006340018A
公开(公告)日：2006-12-14
申请号：JP2005162034
申请日：2005-06-01
申请人： Sony Corp , ソニー株式会社
发明人： SEGAMI MASAHIRO , KAWABE AZUMA , HIROTA ISAO
IPC分类号： H04N5/225 , H01L21/339 , H01L29/762 , H04N101/00
摘要： PROBLEM TO BE SOLVED: To reduce interference across the drive power voltage, when two or more drive power voltages are applied to a capacitive load such as a CCD. SOLUTION: An impedance controller (delay lines 56 and 57, and an impedance distributed switch groups 58 and 59) for controlling output impedance of an output voltage Vout is arranged so as to reduce impedance with progress of time, according to transfer characteristics of a CCD 60 of capacitive load. A transients speed of the output voltage Vout is set at a low speed. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：当将两个或更多个驱动电源电压施加到诸如CCD的电容性负载时，为了减少驱动电源电压的干扰。解决方案：用于控制输出电压Vout的输出阻抗的阻抗控制器（延迟线56和57以及阻抗分布开关组58和59）被布置成随着时间的推移而减小阻抗，根据传输特性的电容性负载的CCD 60。输出电压Vout的瞬变速度被设定为低速。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2003046352A Variable gain amplifier 审中-公开
标题翻译：可变增益放大器
公开(公告)号：JP2003046352A
公开(公告)日：2003-02-14
申请号：JP2001230947
申请日：2001-07-31
申请人： Sony Corp , ソニー株式会社
发明人： KAWABE AZUMA
IPC分类号： H03G3/10
摘要： PROBLEM TO BE SOLVED: To provide a variable gain amplifier that can dramatically widen a variable gain range.
SOLUTION: The variable gain amplifier is provided with: an input differential pair circuit 61 that has a plurality of differential pair FETs (N1 to N4) each comprising a couple of FETs and acts like a V/I converter that converts an input voltage (Vin) into a current; an output differential pair circuit 62 that has a plurality of differential pair FETs (N5 to N8) each comprising a couple of FETs and acts like an I/V converter for converting the converted current into an output voltage (Vo); a control bias generating circuit K1 that control currents flowing through the differential pair FETs by using bias voltages Bias 1, Bias 2; selector switches SW1 to SW4 that select whether a current may be supplied to the input and output differential pair circuits via current source FETs N9 to N12; and a differential pair size switching control circuit K2 that selects the switches to control the size of the input differential pairs and the size of the output differential pairs.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供可以显着拓宽可变增益范围的可变增益放大器。解决方案：可变增益放大器提供有：输入差分对电路61，其具有多个差分对FET（N1至N4），每个差分对FET（N1至N4）均包含一对FET，并且像V / I转换器一样工作，V / I转换器将输入电压（Vin ）成当前具有多个差分对FET（N5〜N8）的输出差分对电路62，每个差分对FET包括一对FET，并且像I / V转换器一样，将转换的电流转换为输出电压（Vo）; 控制偏压发生电路K1，其通过使用偏置电压Bias 1，Bias 2来控制流过差分对FET的电流; 选择开关SW1〜SW4，选择是否可以经由电流源FET N9〜N12将电流供给到输入输出差分对电路; 以及选择开关来控制输入差分对的大小和输出差分对的大小的差分对大小切换控制电路K2。

3. 发明专利

JP2007221403A Drive circuit for charge transfer part, driving method and charge transfer system 有权
标题翻译：充电传输部分的驱动电路，驱动方法和充电传输系统
公开(公告)号：JP2007221403A
公开(公告)日：2007-08-30
申请号：JP2006038795
申请日：2006-02-16
申请人： Sony Corp , ソニー株式会社
发明人： KAWABE AZUMA , KAKIOKA HIDENOBU , FUKUOKA FUMIAKI , HIROTA ISAO , SEGAMI MASAHIRO , KINUGASA YUKIHISA
IPC分类号： H01L27/148 , H04N5/335 , H04N5/341 , H04N5/365 , H04N5/369 , H04N5/3728 , H04N5/376
CPC分类号： H04N5/3765 , H04N5/372 , H04N5/37213
摘要： PROBLEM TO BE SOLVED: To reduce interference between two or more drive voltages applied to a load such as a CCD.
SOLUTION: A drive circuit has a driving mode for outputting current from a certain reference current through current mirror circuits CM1, CM2 when two or more drive voltages are applied to the load such as a CCD, and the current is slowly switched at a certain optional time constant by time constant circuits 540, 541. Consequently, the transient speed of voltage Vout which is a drive voltage is decreased and the interference between the drive voltages is reduced.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：减少施加到诸如CCD的负载的两个或更多个驱动电压之间的干扰。解决方案：当将两个或多个驱动电压施加到诸如CCD的负载时，驱动电路具有用于从某一参考电流输出电流通过电流镜电路CM1，CM2的驱动模式，并且电流缓慢地切换通过时间常数电路540,541的一定的可选时间常数。因此，作为驱动电压的电压Vout的瞬态速度降低，并且驱动电压之间的干扰减小。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2006196105A Sample-and-hold circuit 有权
标题翻译：样品保持电路
公开(公告)号：JP2006196105A
公开(公告)日：2006-07-27
申请号：JP2005007551
申请日：2005-01-14
申请人： Sony Corp , ソニー株式会社
发明人： KAWABE AZUMA
IPC分类号： G11C27/00 , H03M1/12
摘要： PROBLEM TO BE SOLVED: To provide a sample-and-hold circuit capable of improving a sampling precision.
SOLUTION: In a first operation mode, voltage in which offset voltage VOFST is subtracted from signal voltage VIN inputted to an input terminal Tin is applied to a capacitor 1. In a second operation mode, voltage VSMP held in the capacitor 1 is inputted to an operational amplifier OP1. Thereby, in the second operation mode, voltage in which the offset voltage VOFST is added to the voltage VSMP held in the capacitor 1 is outputted from the operational amplifier OP1. At this time, since the voltage VSMP in which the offset voltage VOFST is subtracted from the signal voltage VIN is held in the capacitor 1, voltage in which the offset voltage VOFST is added to the above mentioned voltage is almost equal to the signal voltage VIN inputted to the input terminal Tin in the first operation mode.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供能够提高采样精度的采样和保持电路。解决方案：在第一操作模式中，将向输入端子Tin输入的信号电压VIN中减去偏移电压VOFST的电压施加到电容器1.在第二操作模式中，保持在电容器1中的电压VSMP为输入到运算放大器OP1。由此，在第二动作模式中，从运算放大器OP1输出将补偿电压VOFST加到保持在电容器1中的电压VSMP的电压。此时，由于从信号电压VIN减去偏移电压VOFST的电压VSMP被保持在电容器1中，所以将偏置电压VOFST加到上述电压的电压几乎等于信号电压VIN 在第一操作模式中输入到输入端子Tin。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2006060505A Pulse drive circuit and pulse ringing suppression circuit 审中-公开
标题翻译：脉冲驱动电路和脉冲环形抑制电路
公开(公告)号：JP2006060505A
公开(公告)日：2006-03-02
申请号：JP2004239917
申请日：2004-08-19
申请人： Sony Corp , ソニー株式会社
发明人： YAMADA KAZUHIRO , HIGUCHI NAOHIRO , KAWABE AZUMA
IPC分类号： H04L25/03
摘要： PROBLEM TO BE SOLVED: To obtain a pulse drive circuit and a pulse ringing suppression circuit capable of effectively suppressing ringing with the ringing suppression circuit by transmitting voltage fluctuations at the time of rising and falling of an input signal when the input signal is drastically changed, for example, in the case of a higher frequency and a higher gain, and also, capable of suppressing the ringing, even when the ringing is changed, by adjusting the ringing suppression circuit with the switching of a control signal of a ringing suppression adjustment circuit, and controlling a gain which transmits the voltage fluctuations of the input signal, and a delay time respectively in the pulse drive circuit and the pulse ringing suppression circuit. SOLUTION: In the pulse drive circuit and the pulse ringing suppression circuit, the ringing suppression circuits 5a, 5b are provided to the pulse drive circuit 1. The ringing occurring in an output waveform is reduced by adding in an alternating mode the rising or the falling of an input pulse to the rising or the falling of the output signal. A delay amount or/and a delay time τ of the ringing suppression circuits 5a, 5b can be adjusted. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：为了获得脉冲驱动电路和脉冲振铃抑制电路，能够通过在输入信号为输入信号时在输入信号的上升和下降时发送电压波动来有效地抑制振铃抑制电路的振铃急剧变化的情况下，例如在频率高，增益较高的情况下，即使振铃改变，也可以通过调节振铃抑制电路来控制振铃的控制信号抑制调节电路，以及分别在脉冲驱动电路和脉冲振铃抑制电路中控制传输输入信号的电压波动的增益和延迟时间。解决方案：在脉冲驱动电路和脉冲振铃抑制电路中，振铃抑制电路5a，5b被提供给脉冲驱动电路1.通过在交替模式中增加上升沿减小输出波形中的振铃或输入脉冲的下降到输出信号的上升或下降。可以调节振铃抑制电路5a，5b的延迟量或/和延迟时间τ。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2005354290A Delay circuit 审中-公开
标题翻译：延时电路
公开(公告)号：JP2005354290A
公开(公告)日：2005-12-22
申请号：JP2004171484
申请日：2004-06-09
申请人： Sony Corp , ソニー株式会社
发明人： KAWABE AZUMA
IPC分类号： H03K5/13 , H03K5/131
摘要： PROBLEM TO BE SOLVED: To stabilize a delay time by a simple circuit constitution.
SOLUTION: A delay circuit comprises a MOS (Metal-Oxide Semiconductor) capacity 23 that has a prescribed gate threshold voltage and stores charge by applying a constant current, a comparison circuit 24 for comparing a gate current value in the MOS capacity 23 with a prescribed threshold voltage for outputting a value corresponding to the compared result, and a MOS transistor 25 that is diode-connected to the comparator 24 and has the same gate threshold voltage as the MOS capacity 23.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过简单的电路结构来稳定延迟时间。解决方案：延迟电路包括具有规定的栅极阈值电压并通过施加恒定电流来存储电荷的MOS（金属氧化物半导体）电容23，用于比较MOS容量23中的栅极电流值的比较电路24 具有用于输出与比较结果相对应的值的规定阈值电压以及二极管连接到比较器24并具有与MOS容量23相同的栅极阈值电压的MOS晶体管25.（C） 2006年，JPO＆NCIPI

7. 发明专利

JP2009232366A Signal processing apparatus 有权
标题翻译：信号处理装置
公开(公告)号：JP2009232366A
公开(公告)日：2009-10-08
申请号：JP2008077787
申请日：2008-03-25
申请人： Sony Corp , ソニー株式会社
发明人： OSHIMA SATORU , SHIMIZU TATSUO , KAWABE AZUMA , KAKIOKA HIDENOBU
IPC分类号： H03K5/00 , G06F1/10 , H03K5/19 , H03K5/26
CPC分类号： H03K5/086 , H03K5/003 , H04L25/4919
摘要： PROBLEM TO BE SOLVED: To correct distortion in the duty cycle of a data signal in which occurrence probabilities of "0" and "1" are different. SOLUTION: A phase detection circuit 21 detects advanced and delayed phases of a data signal in which occurrence probabilities of "0" and "1" are different. An AND circuit 43 detects rising of the data signal and an AND circuit 44 detects falling. A +DCD detection circuit 45 detects distortion at a plus side of duty cycle based on detection results of the phase detection circuit 21 and the AND circuits 43 and 44, and a -DCD detection circuit 46 detects distortion at a minus side of duty cycle. A duty adjustment circuit 12 adjusts the duty cycle based on detection results of the +DCD detection circuit 45 and the -DCD detection circuit 46, thereby correcting the distortion of duty cycle. The present invention may be applicable to e.g., a receiving apparatus that receives a data signal. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：校正其中“0”和“1”的发生概率不同的数据信号的占空比中的失真。解决方案：相位检测电路21检测“0”和“1”的发生概率不同的数据信号的高级和延迟相位。 AND电路43检测数据信号的上升，AND电路44检测到下降。 A + DCD检测电路45基于相位检测电路21和AND电路43和44的检测结果来检测占空比的正侧的失真，并且-DCD检测电路46检测占空比的负侧的失真。占空比调整电路12基于+ DCD检测电路45和-DCD检测电路46的检测结果调整占空比，从而校正占空比的失真。本发明可以适用于例如接收数据信号的接收装置。版权所有（C）2010，JPO＆INPIT

8. 发明专利

JP2003060508A Delta sigma modulator 审中-公开
标题翻译： DELTA SIGMA调制器
公开(公告)号：JP2003060508A
公开(公告)日：2003-02-28
申请号：JP2001247338
申请日：2001-08-16
申请人： Sony Corp , ソニー株式会社
发明人： KAWABE AZUMA
IPC分类号： H03M3/02
摘要： PROBLEM TO BE SOLVED: To provide a delta sigma modulator that can change a plurality of sampling frequencies for use, avoid variation in a zero-point frequency due to the switching of the sampling frequencies, and reduce quantization noise.
SOLUTION: In the delta sigma modulator including integrators 10, 20, and 30 connected in series and a quantizer 40, multipliers 111 and 110 where multiplication coefficients f1 and f2 are set according to a sampling frequency, and selectors 50 and 60 for selecting the multipliers are provided, the output of the integrator 20 is multiplied by a predetermined multiplication coefficient f1 or f2 by the multiplier that is selected according to the sampling frequency, and the multiplied result is feedback to the integrator 10 at the first stage, thus maintaining a zero-point frequency to a nearly fixed value without being affected by the switching of the sampling frequency, and hence reducing quantization noise.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：为了提供可以改变多个采样频率以供使用的Δ-Σ调制器，避免由于采样频率的切换引起的零点频率的变化，并且减少量化噪声。解决方案：包括串联连接的积分器10,20和30的三角Σ调制器和量化器40，乘法器111和110，乘法系数f1和f2根据采样频率设置，选择器50和60用于选择乘法器，则通过根据采样频率选择的乘法器将积分器20的输出乘以预定的乘法系数f1或f2，并将相乘的结果在第一级反馈到积分器10，从而保持零而不受采样频率切换的影响，从而降低了量化噪声。

9. 发明专利

JPH09307368A COMMON-MODE SIGNAL DETECTING CIRCUIT 失效
公开(公告)号：JPH09307368A
公开(公告)日：1997-11-28
申请号：JP14075996
申请日：1996-05-10
申请人： SONY CORP
发明人： KAWABE AZUMA , IZUMIHARA KUNIHIKO
IPC分类号： H03K5/1252 , H03D13/00 , H03F3/34 , H03F3/45 , H03K5/26
摘要： PROBLEM TO BE SOLVED: To suppress current consumption to be small and to input so far as a signal of a large amplitude. SOLUTION: A common-mode signal detection circuit voltage-current-converts input signal voltages V+ and V- inputted to signal input terminals 11 and 12 by FETM7 and M8 through the use of output conductance to sum up the currents obtained by this, and FETM18 current-voltage-converts it to generate voltage Vn3 . In addition, the common-mode signal detection circuit generates a common-mode signal V0 of a value corresponding to a difference between Vn3 and voltage Vref fixed according to reference voltage by a differential amplifier consisting of M9 , M16 , M17 , M19 and M20 .

10. 发明专利

JPH09130253A MULTI-CHANNEL A/D CONVERTER AND DIGITAL SIGNAL PROCESSOR 失效
公开(公告)号：JPH09130253A
公开(公告)日：1997-05-16
申请号：JP30849895
申请日：1995-11-02
申请人： SONY CORP
发明人： YANARI MASAHARU , KAWAI EIJI , TAGAMI SHIGEO , KAWABE AZUMA
IPC分类号： H03M3/02
摘要： PROBLEM TO BE SOLVED: To easily adjust the gain of digital signals outputted from a multi-channel A/D converter. SOLUTION: Analog signals are converted into the digital signals by ΔΣmodulators 3a and 3b and digital decimation filters 4a and 4b, a prescribed coefficient is multiplied with the digital signals outputted from the digital decimation filters 4a and 4b in multipliers 5a and 5b and thus, the output level of the digital signals outputted from this multi-channel A/D converter is optimally adjusted.

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