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    • 1. 发明专利
    • Semiconductor device
    • 半导体器件
    • JP2013051421A
    • 2013-03-14
    • JP2012206132
    • 2012-09-19
    • Sharp Corpシャープ株式会社
    • CHIKAMA YOSHIMASANISHIKI HIROHIKOOTA AYAFUMIMIZUNO YUJIHARA TAKESHIAIDA TETSUYASUZUKI MASAHIKOTAKEI MICHIKONAKAGAWA OKIFUMIHARUMOTO YOSHIMASA
    • H01L21/768G02F1/1345G02F1/1368G09F9/30H01L21/28H01L21/336H01L23/522H01L29/417H01L29/786
    • H01L27/1225G02F1/13458G02F1/136213H01L27/124H01L27/1244H01L27/1248
    • PROBLEM TO BE SOLVED: To control a tapered shape of a contact hole in a terminal part with high accuracy.SOLUTION: A semiconductor device comprises: a thin film transistor including an oxide semiconductor layer 7a, a source wiring 13as and a drain electrode 13ad; and a terminal part including a first connection part 3c, a second connection part 13c and a third connection part 19c formed on the second connection part. The second connection part contacts the first connection part in a first opening provided in first and second insulation films 5,9. The third connection part 19c contacts the second connection part in a second opening provided in a protection film 15. The first opening is formed by simultaneously etching the first insulation film 5 and the second insulation film 9. The second opening is formed by etching the protection film 15 separately from the first and second insulation film. The second connection part 13c covers end faces of the first and the second insulation films in the first opening and not covers an end face of the protection film 15 in the second opening.
    • 要解决的问题:以高精度控制端子部分中的接触孔的锥形形状。 解决方案:半导体器件包括:薄膜晶体管,其包括氧化物半导体层7a,源极布线13as和漏极13ad; 以及包括形成在第二连接部上的第一连接部3c,第二连接部13c和第三连接部19c的端子部。 第二连接部分在设置在第一和第二绝缘膜5,9中的第一开口中接触第一连接部分。 第三连接部分19c在设置在保护膜15中的第二开口中与第二连接部分接触。第一开口通过同时蚀刻第一绝缘膜5和第二绝缘膜9而形成。第二开口通过蚀刻保护 薄膜15与第一和第二绝缘薄膜分开。 第二连接部13c覆盖第一开口中的第一绝缘膜和第二绝缘膜的端面,并且不覆盖第二开口中的保护膜15的端面。 版权所有(C)2013,JPO&INPIT
    • 2. 发明专利
    • Active matrix substrate and liquid crystal display
    • 活性基质和液晶显示
    • JP2010128323A
    • 2010-06-10
    • JP2008304732
    • 2008-11-28
    • Sharp Corpシャープ株式会社
    • HARA TAKESHICHIKAMA YOSHIMASANAKAGAWA OKIFUMINAKANO YUYANAKAMURA WATARUKITO KENICHITANAKA AKINORI
    • G02F1/1368G09F9/30H01L21/3205H01L21/768H01L23/52H01L29/786
    • PROBLEM TO BE SOLVED: To provide constitution that metal included in a wiring line is not corroded even when a defect is caused in an electrode terminal in the connection part of the wiring line and the electrode terminal in an active matrix substrate.
      SOLUTION: In the active matrix substrate including the connection part 16, the connection part 16 includes a first metal layer 1b, a second metal layer 1a layered on the first metal layer 1b so as to be narrower than the width of the first metal layer 1b, a protective part 2 layered on the second metal layer 1a so as to completely cover the second metal layer 1a and to be narrower than the width of the first metal layer 1b, and the electrode terminal 3 layered on the protective part 2 so as to completely cover the protective part 2 and to come in contact with the first metal layer 1b. Thereby, the metal included in the wiring line is not corroded even when a defective part 4 is caused in the electrode terminal 3.
      COPYRIGHT: (C)2010,JPO&INPIT
    • 要解决的问题:即使当在有源矩阵基板中的布线和连接部分的电极端子中的电极端子发生缺陷时,提供布线中包含的金属也不被腐蚀的结构。 解决方案:在包括连接部16的有源矩阵基板中,连接部16包括第一金属层1b,第一金属层1b上形成的第二金属层1a,其比第一金属层1b的宽度窄。 金属层1b,层叠在第二金属层1a上的保护部2,以完全覆盖第二金属层1a,并且比第一金属层1b的宽度窄;以及层叠在保护部2上的电极端子3 以完全覆盖保护部分2并与第一金属层1b接触。 因此,即使在电极端子3中产生有缺陷的部分4,包括在布线中的金属也不被腐蚀。(C)2010,JPO&INPIT
    • 5. 发明专利
    • Thin-film transistor substrate, and method of manufacturing the same
    • 薄膜晶体管基板及其制造方法
    • JP2010243594A
    • 2010-10-28
    • JP2009089376
    • 2009-04-01
    • Sharp Corpシャープ株式会社
    • CHIKAMA YOSHIMASANAKAGAWA OKIFUMIHARA TAKESHINISHIKI HIROHIKO
    • G02F1/1368H01L21/336H01L29/786
    • PROBLEM TO BE SOLVED: To increase the capacitance of an auxiliary capacitor formed on a substrate, and to prevent the fluctuation thereof.
      SOLUTION: When forming the semiconductor layers 13, 17 of a TFT substrate 1 provided with a TFT 4 and the auxiliary capacitor 5, IGZO whose main components are indium, gallium, zinc and oxygen is used. When manufacturing the TFT substrate 1, as processing for reducing the resistance of the auxiliary capacitor semiconductor layer 17, plasma processing is performed after forming a passivation layer 20 and before forming a pixel electrode 21. Thus, the auxiliary capacitor semiconductor layer 17 is made into a conductor, the capacitance of the auxiliary capacitor 5 is increased, and the capacitor fluctuation of the auxiliary capacitor 5 is prevented.
      COPYRIGHT: (C)2011,JPO&INPIT
    • 要解决的问题:增加形成在基板上的辅助电容器的电容,并防止其波动。 解决方案:当形成设置有TFT 4的TFT基板1和辅助电容器5的半导体层13,17时,使用主要成分为铟,镓,锌和氧的IGZO。 当制造TFT基板1时,作为用于降低辅助电容器半导体层17的电阻的处理,在形成钝化层20之后和形成像素电极21之前进行等离子体处理。因此,辅助电容器半导体层17被制成 导体,辅助电容器5的电容增加,并且防止了辅助电容器5的电容器波动。 版权所有(C)2011,JPO&INPIT
    • 8. 发明专利
    • Manufacturing method of transistor
    • 晶体管的制造方法
    • JP2004349583A
    • 2004-12-09
    • JP2003146907
    • 2003-05-23
    • Masashi KawasakiHideo OnoSharp Corpシャープ株式会社英男 大野雅司 川崎
    • HARA TAKESHIFUJITA TATSUYAOCHI HISAOYOSHIOKA HIROTOSUGIHARA TOSHINORIKAWASAKI MASASHIONO HIDEO
    • H01L29/786H01L21/336
    • PROBLEM TO BE SOLVED: To provide a method of manufacturing a bottom gate type transistor without damaging zinc oxide and without deteriorating indication quality using an ink jet method which is simple in operation and advantageous in cost when the zinc oxide is employed as a semiconductor element. SOLUTION: The manufacturing method of a bottom gate type transistor is adapted such that a gate electrode 11 is formed on a glass substrate 10 into a predetermined shape, and then a gate insulating film 12 is laminated, on which film 12 a source electrode 13 and a drain electrode 14 are in turn disposed. In the manufacturing method, the source electrode 13 and the drain electrode 14 are formed into predetermined shapes, and then a channel layer 15 containing the zinc oxide is formed into a predetermined shape with an ink jet method. COPYRIGHT: (C)2005,JPO&NCIPI
    • 解决的问题:提供一种制造底栅型晶体管的方法,而不损害氧化锌并且不会使用使用简单操作的喷墨方法而劣化指示质量,并且当将氧化锌用作 半导体元件。 解决方案:底栅型晶体管的制造方法适于使得栅极电极11形成在玻璃基板10上成为预定形状,然后层叠栅极绝缘膜12,其上膜12为源极 电极13和漏电极14依次设置。 在制造方法中,将源电极13和漏电极14形成为规定的形状,然后利用喷墨法将含有氧化锌的沟道层15形成为规定的形状。 版权所有(C)2005,JPO&NCIPI